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1. 发明授权

US08015429B2 Clock and data recovery (CDR) method and apparatus 有权
标题翻译：时钟和数据恢复（CDR）方法和设备
公开(公告)号：US08015429B2
公开(公告)日：2011-09-06
申请号：US12165428
申请日：2008-06-30
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04 , H03K9/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

2. 发明授权

US08375242B2 Clock and data recovery (CDR) method and apparatus 有权
标题翻译：时钟和数据恢复（CDR）方法和设备
公开(公告)号：US08375242B2
公开(公告)日：2013-02-12
申请号：US13196871
申请日：2011-08-02
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04 , H04L27/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

3. 发明申请

US20110289341A1 CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS 有权
标题翻译：时钟和数据恢复（CDR）方法和装置
公开(公告)号：US20110289341A1
公开(公告)日：2011-11-24
申请号：US13196871
申请日：2011-08-02
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

4. 发明申请

US20090327788A1 CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS 有权
标题翻译：时钟和数据恢复（CDR）方法和装置
公开(公告)号：US20090327788A1
公开(公告)日：2009-12-31
申请号：US12165428
申请日：2008-06-30
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

5. 发明授权

US07289557B2 Adaptive equalization using a conditional update sign-sign least mean square algorithm 有权
标题翻译：使用条件更新符号最小均方算法进行自适应均衡
公开(公告)号：US07289557B2
公开(公告)日：2007-10-30
申请号：US10660228
申请日：2003-09-10
申请人： Ganesh Balamurugan , Bryan K. Casper , James E. Jaussi , Stephen R. Mooney
发明人： Ganesh Balamurugan , Bryan K. Casper , James E. Jaussi , Stephen R. Mooney
IPC分类号： H03D3/22 , H04L27/22
CPC分类号： H03H21/0043 , H03H21/0001 , H03H2021/0065 , H04L25/03038 , H04L25/03885 , H04L2025/03477 , H04L2025/03617
摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h(t+1)= h(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{ x(t)}, where h(t) is the filter vector representing the filter taps of the FIR filter, x(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.
摘要翻译：用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器：<？in-line-formula description =“In-line 公式“end =”lead“？> h（t + 1）= h（t）+ mu [sgn {d（t）} - t）-Kd（t）}] sgn { x（t）}，<？in-line-formula description =“In-line Formulas”end =“tail”？> OSTYLE =“SINGLE”> h（t）是表示FIR滤波器的滤波器抽头的滤波器向量，x（t）是表示接收数据的当前和过去采样的数据x（t） t），d（t）是用于训练的期望数据，z（t）是FIR滤波器的输出，mu决定适配的存储器或窗口大小，K是考虑到实际限制的比例因子通信信道，接收机和均衡器。此外，提供了用于校准比例因子K的过程和电路结构。

6. 发明申请

US20080238503A1 Injection locked LC VCO clock deskewing 有权
标题翻译：注入锁定LC VCO时钟去歪斜
公开(公告)号：US20080238503A1
公开(公告)日：2008-10-02
申请号：US11731776
申请日：2007-03-30
申请人： Mozhgan Mansuri , Sudip Shekhar , Bryan K. Casper , Frank P. O'Mahony
发明人： Mozhgan Mansuri , Sudip Shekhar , Bryan K. Casper , Frank P. O'Mahony
IPC分类号： H03L7/08
CPC分类号： H03L7/24 , H04L7/0008 , H04L7/0037 , H04L7/0276
摘要： In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock.
摘要翻译：通常，在一个方面，本公开描述了一种包括感应电容性压控振荡器（LC VCO）以产生输出时钟的装置。电压/电流转换器用于接收转发的时钟并将转发的时钟注入LC VCO。输出时钟是转发时钟的偏斜版本。

7. 发明授权

US07286006B2 Sign-sign least means square filter 有权
标题翻译：符号最小的意思是方形滤波器
公开(公告)号：US07286006B2
公开(公告)日：2007-10-23
申请号：US10879417
申请日：2004-06-28
申请人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
发明人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
IPC分类号： H03K5/00
CPC分类号： H03H21/0043 , H03H21/0001 , H03H2021/0065
摘要： In some embodiments, an adaptive filter employs two adaptation modes, where during one adaptation mode the adaptive filter is updated only when the received training sample is a first binary value and during the other adaptation mode the adaptive filter is updated only when the received sample is a second binary value. Each adaptation mode provides a set of filter weights, and these two sets of filter weights are averaged to provide an adapted set of filter weights. The use of two adaptation mode allows for a clock boundary in which the digital portion of the filter operates at a lower clock rate than the analog portion. In other embodiments, a filter architecture is described for providing the algebraic signs of the received data samples, important for sign-sign least means square filtering algorithms. In other embodiments, a filter architecture is described in which efficient use is made of voltage-to-current converters so as to achieve a high throughput rate during filtering. Embodiments of the present invention have application to channel equalization.
摘要翻译：在一些实施例中，自适应滤波器采用两种适应模式，其中在一个自适应模式期间，只有当所接收的训练样本是第一二进制值时才自动滤波器被更新，并且在另一自适应模式期间，仅当所接收的样本是第二个二进制值。每个适配模式提供一组滤波器权重，并且将这两组滤波器权重进行平均以提供一组适用的滤波器权重。使用两个适配模式允许滤波器的数字部分以比模拟部分更低的时钟速率工作的时钟边界。在其他实施例中，描述了用于提供接收数据样本的代数符号的滤波器架构，对于符号最小均方滤波算法而言是重要的。在其他实施例中，描述了一种滤波器架构，其中有效地使用电压 - 电流转换器，以便在滤波期间实现高吞吐率。本发明的实施例具有对信道均衡的应用。

8. 发明授权

US07650271B2 Time-domain device noise simulator 失效
标题翻译：时域设备噪声模拟器
公开(公告)号：US07650271B2
公开(公告)日：2010-01-19
申请号：US11395537
申请日：2006-03-31
申请人： Frank P. O'Mahony , Haydar Kutuk , Bryan K. Casper , Eyal Fayneh , Sivakumar Mudanai , Wei-kai Shih , Farag Fattouh
发明人： Frank P. O'Mahony , Haydar Kutuk , Bryan K. Casper , Eyal Fayneh , Sivakumar Mudanai , Wei-kai Shih , Farag Fattouh
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.
摘要翻译：通常，在一个方面，本公开描述了一种用于在时域电路仿真中模拟各种类型的器件噪声的模拟器。模拟器能够为晶体管以及无源元件（如电阻）增加噪声。模拟器使用与设备并联的至少一个电流源来模拟噪声。电流源产生随机电流输出以根据随机高斯数和器件噪声的标准偏差来模拟器件噪声。可以基于在该模拟时间和更新时间具有特定偏压的装置的噪声功率谱密度来确定噪声标准偏差。模拟器能够通过利用具有不同更新步骤的多个电流源来模拟具有恒定或单调降低的噪声频谱（例如，热噪声，闪烁噪声）的任何噪声源。模拟器与标准电路模拟器兼容。

9. 发明授权

US07529296B2 Adaptive equalization method and circuit for continuous run-time adaptation 有权
标题翻译：用于连续运行时适应的自适应均衡方法和电路
公开(公告)号：US07529296B2
公开(公告)日：2009-05-05
申请号：US11232492
申请日：2005-09-21
申请人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
发明人： James E. Jaussi , Bryan K. Casper , Ganesh Balamurugan , Stephen R. Mooney
IPC分类号： H03K5/159
CPC分类号： H04L25/03057 , H04L2025/03598 , H04L2025/03681
摘要： In some embodiments disclosed herein, equalizers in a receiver are adapted during normal operation, as they extract bit data from a received bit stream, to account for channel and/or circuit fluctuations.
摘要翻译：在本文公开的一些实施例中，接收机中的均衡器在正常操作期间被适配，因为它们从接收到的比特流中提取比特数据，以解决信道和/或电路波动。

10. 发明授权

US07313181B2 Calibration of scale factor in adaptive equalizers 有权
标题翻译：自适应均衡器中比例因子校准
公开(公告)号：US07313181B2
公开(公告)日：2007-12-25
申请号：US10660415
申请日：2003-09-10
申请人： Ganesh Balamurugan , Bryan K. Casper , James E. Jaussi , Stephen R. Mooney
发明人： Ganesh Balamurugan , Bryan K. Casper , James E. Jaussi , Stephen R. Mooney
IPC分类号： H03H7/30 , G06F17/10
CPC分类号： H04L25/03038 , H03H21/0001 , H03H2021/0065 , H04L2025/03477
摘要： An adaptive equalizer finite impulse response (FIR) filter for high-speed communication channels with modest complexity, where the filter is iteratively updated during a training sequence by a circuit performing the update: h(t+1)= h(t)+μ[sgn{d(t)}−sgn{z(t)−Kd(t)}]sgn{ x(t)}, where h(t) is the filter vector representing the filter taps of the FIR filter, x(t) is the data vector representing present and past samples of the received data x(t), d(t) is the desired data used for training, z(t) is the output of the FIR filter, μ determines the memory or window size of the adaptation, and K is a scale factor taking into account practical limitations of the communication channel, receiver, and equalizer. Furthermore, a procedure and circuit structure is provided for calibrating the scale factor K.
摘要翻译：用于具有适度复杂度的高速通信信道的自适应均衡器有限脉冲响应（FIR）滤波器，其中通过执行更新的电路在训练序列期间迭代地更新滤波器： h（t + 1 ）= h（t）+ mu [sgn {d（t-sgn {z（t）-Kd（t）sgn { x（t）}，其中 h（t）是表示FIR滤波器的滤波器抽头的滤波器向量， x（t）是表示接收到的当前和过去样本的数据向量数据x（t），d（t）是用于训练的期望数据，z（t）是FIR滤波器的输出，μ确定适配的存储器或窗口大小，K是考虑到的比例因子通信信道，接收机和均衡器的实际限制。此外，提供了用于校准比例因子K的过程和电路结构。

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