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1. 发明申请

US20080238503A1 Injection locked LC VCO clock deskewing 有权
标题翻译：注入锁定LC VCO时钟去歪斜
公开(公告)号：US20080238503A1
公开(公告)日：2008-10-02
申请号：US11731776
申请日：2007-03-30
申请人： Mozhgan Mansuri , Sudip Shekhar , Bryan K. Casper , Frank P. O'Mahony
发明人： Mozhgan Mansuri , Sudip Shekhar , Bryan K. Casper , Frank P. O'Mahony
IPC分类号： H03L7/08
CPC分类号： H03L7/24 , H04L7/0008 , H04L7/0037 , H04L7/0276
摘要： In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock.
摘要翻译：通常，在一个方面，本公开描述了一种包括感应电容性压控振荡器（LC VCO）以产生输出时钟的装置。电压/电流转换器用于接收转发的时钟并将转发的时钟注入LC VCO。输出时钟是转发时钟的偏斜版本。

2. 发明授权

US07683729B2 Injection locked LC VCO clock deskewing 有权
标题翻译：注入锁定LC VCO时钟去歪斜
公开(公告)号：US07683729B2
公开(公告)日：2010-03-23
申请号：US11731776
申请日：2007-03-30
申请人： Mozhgan Mansuri , Sudip Shekhar , Bryan K. Casper , Frank P. O'Mahony
发明人： Mozhgan Mansuri , Sudip Shekhar , Bryan K. Casper , Frank P. O'Mahony
IPC分类号： H03K3/282
CPC分类号： H03L7/24 , H04L7/0008 , H04L7/0037 , H04L7/0276
摘要： In general, in one aspect, the disclosure describes an apparatus that includes an inductive capacitive voltage controlled oscillator (LC VCO) to generate an output clock. A voltage to current converter is used to receive a forwarded clock and to inject the forwarded clock to the LC VCO. The output clock is a deskewed version of the forwarded clock.
摘要翻译：通常，在一个方面，本公开描述了一种包括感应电容性压控振荡器（LC VCO）以产生输出时钟的装置。电压/电流转换器用于接收转发的时钟并将转发的时钟注入LC VCO。输出时钟是转发时钟的偏斜版本。

3. 发明授权

US08015429B2 Clock and data recovery (CDR) method and apparatus 有权
标题翻译：时钟和数据恢复（CDR）方法和设备
公开(公告)号：US08015429B2
公开(公告)日：2011-09-06
申请号：US12165428
申请日：2008-06-30
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04 , H03K9/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

4. 发明授权

US07650271B2 Time-domain device noise simulator 失效
标题翻译：时域设备噪声模拟器
公开(公告)号：US07650271B2
公开(公告)日：2010-01-19
申请号：US11395537
申请日：2006-03-31
申请人： Frank P. O'Mahony , Haydar Kutuk , Bryan K. Casper , Eyal Fayneh , Sivakumar Mudanai , Wei-kai Shih , Farag Fattouh
发明人： Frank P. O'Mahony , Haydar Kutuk , Bryan K. Casper , Eyal Fayneh , Sivakumar Mudanai , Wei-kai Shih , Farag Fattouh
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： In general, in one aspect, the disclosure describes a simulator for emulating various types of device noise in time-domain circuit simulations. The simulator is capable of adding noise to transistors as well as passive elements like resistors. The simulator utilizes at least one current source in parallel to a device to emulate the noise. The current source generates a random current output to emulate the device noise based on a random Gaussian number and the standard deviation of the device noise. The noise standard deviation can be determined based on the noise power spectral density of the device having a particular bias at that simulation time and the update time. The simulator is capable of emulating any noise source with a constant or monotonically decreasing noise spectrum (e.g., thermal noise, flicker noise) by utilizing multiple current sources having different update steps. The simulator is compatible with standard circuit simulators.
摘要翻译：通常，在一个方面，本公开描述了一种用于在时域电路仿真中模拟各种类型的器件噪声的模拟器。模拟器能够为晶体管以及无源元件（如电阻）增加噪声。模拟器使用与设备并联的至少一个电流源来模拟噪声。电流源产生随机电流输出以根据随机高斯数和器件噪声的标准偏差来模拟器件噪声。可以基于在该模拟时间和更新时间具有特定偏压的装置的噪声功率谱密度来确定噪声标准偏差。模拟器能够通过利用具有不同更新步骤的多个电流源来模拟具有恒定或单调降低的噪声频谱（例如，热噪声，闪烁噪声）的任何噪声源。模拟器与标准电路模拟器兼容。

5. 发明授权

US08375242B2 Clock and data recovery (CDR) method and apparatus 有权
标题翻译：时钟和数据恢复（CDR）方法和设备
公开(公告)号：US08375242B2
公开(公告)日：2013-02-12
申请号：US13196871
申请日：2011-08-02
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04 , H04L27/00
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

6. 发明申请

US20110289341A1 CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS 有权
标题翻译：时钟和数据恢复（CDR）方法和装置
公开(公告)号：US20110289341A1
公开(公告)日：2011-11-24
申请号：US13196871
申请日：2011-08-02
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12 , G06F1/04
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

7. 发明申请

US20090327788A1 CLOCK AND DATA RECOVERY (CDR) METHOD AND APPARATUS 有权
标题翻译：时钟和数据恢复（CDR）方法和装置
公开(公告)号：US20090327788A1
公开(公告)日：2009-12-31
申请号：US12165428
申请日：2008-06-30
申请人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
发明人： Ganesh Balamurugan , Frank P. O'Mahony , Bryan K. Casper
IPC分类号： G06F1/12
CPC分类号： H04L7/0337 , H03L7/0814 , H03L7/091 , H04L7/0004
摘要： Embodiments of methods and apparatus for clock and data recovery are disclosed. In some embodiments, a method for recovering data from an input data stream of a device is disclosed, the method comprising synchronizing, during an initialization phase, a data clock (DCK) with an input data stream; synchronizing, during the initialization phase, an edge clock signal (ECK) with the input data stream based at least in part on a phase relationship between the ECK and the synchronized DCK; and sampling, during the initialization phase, a rising edge of the input data stream with the synchronized ECK to generate a transition level reference voltage. Additional variants and embodiments may also be disclosed and claimed.
摘要翻译：公开了用于时钟和数据恢复的方法和装置的实施例。在一些实施例中，公开了一种用于从设备的输入数据流恢复数据的方法，所述方法包括在初始化阶段期间使具有输入数据流的数据时钟（DCK）同步; 在所述初始化阶段期间，使所述输入数据流的边缘时钟信号（ECK）至少部分地基于所述ECK和所述同步DCK之间的相位关系同步; 并且在初始化阶段期间，利用同步的ECK对输入数据流的上升沿进行采样，以产生转换电平参考电压。也可以公开和要求保护附加的变型和实施例。

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