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1. 发明授权

US06831346B1 Buried layer substrate isolation in integrated circuits 有权
标题翻译：集成电路中埋地层衬底隔离
公开(公告)号：US06831346B1
公开(公告)日：2004-12-14
申请号：US09849047
申请日：2001-05-04
申请人： Gabriel Li , Kenelm G. D. Murray , Jose Arreola , Shahin Sharifzadeh , K. Nirmal Ratnakumar
发明人： Gabriel Li , Kenelm G. D. Murray , Jose Arreola , Shahin Sharifzadeh , K. Nirmal Ratnakumar
IPC分类号： H01L2900
CPC分类号： H01L29/41758 , H01L21/761 , H01L21/823878 , H01L29/0847
摘要： In an embodiment of an integrated circuit structure having buried layer substrate isolation and a method for forming same, a buried layer having conductivity type opposite to that of an overlying well region is used for wells containing transistors prone to noise generation, where the wells are of the same conductivity type as the substrate. The buried layer may in some embodiments include a first portion underlying the transistor and a second portion spaced apart from and laterally surrounding the first portion. In some embodiments, the circuit may include a doped annular region of the same conductivity type as the buried layer, where the annular region contacts a portion of the buried layer and laterally surrounds the transistor. The circuit may further include metallization adapted to connect the well and annular region to opposite polarities of a power supply voltage, or in some embodiments to preclude such connection.
摘要翻译：在具有掩埋层衬底隔离的集成电路结构及其形成方法的实施例中，具有与上覆阱区相反的导电类型的掩埋层用于容纳产生噪声的晶体管的阱，其中阱为与基片相同的导电类型。在一些实施例中，掩埋层可以包括晶体管下面的第一部分和与第一部分间隔开并横向包围第一部分的第二部分。在一些实施例中，电路可以包括与埋层相同的导电类型的掺杂环形区域，其中环形区域接触掩埋层的一部分并横向围绕晶体管。电路还可以包括适于将阱和环形区域连接到电源电压的相反极性的金属化，或者在一些实施例中以排除这种连接。

2. 发明授权

US5959889A Counter-bias scheme to reduce charge gain in an electrically erasable cell 失效
标题翻译：减少电可擦除电池中电荷增益的偏压方案
公开(公告)号：US5959889A
公开(公告)日：1999-09-28
申请号：US998258
申请日：1997-12-29
申请人： K. Nirmal Ratnakumar
发明人： K. Nirmal Ratnakumar
IPC分类号： G11C16/26 , G11C16/04
CPC分类号： G11C16/26
摘要： A counter-bias scheme to reduce or eliminate charge gain in a single-poly or double-poly electrically erasable (E.sup.2) cell having separate program and read transistors which may be configured as a 6-wire cell includes applying a counter-bias voltage to the drain of a program select transistor of the E.sup.2 cell during a read operation. The counter-bias voltage may be approximately equal to a voltage on the floating gate of the cell during the read operation. The present scheme reduces the threshold voltage shifts which may otherwise be experienced in the cell during continuous read operations. In particular, the counter-bias voltage acts to reduce the electric field across the tunnel oxide of the program select transistor, thus reducing the charge gain on the floating gate.
摘要翻译：一种用于减少或消除具有可被配置为6线单元的单独的程序和读取晶体管的单多晶硅或双重多晶硅电可擦除（E2）单元中的电荷增益的反偏压方案包括：将反偏压施加到在读取操作期间E2单元的编程选择晶体管的漏极。在读取操作期间，反偏压可以近似等于电池的浮动栅极上的电压。本方案减少了在连续读取操作期间可能在单元中经历的阈值电压偏移。特别地，反向偏置电压用于减小编程选择晶体管的隧道氧化物两端的电场，从而降低浮动栅极上的电荷增益。

3. 发明授权

US6114724A Nonvolatile semiconductor memory cell with select gate 失效
标题翻译：具有选择栅极的非易失性半导体存储单元
公开(公告)号：US6114724A
公开(公告)日：2000-09-05
申请号：US052770
申请日：1998-03-31
申请人： K. Nirmal Ratnakumar
发明人： K. Nirmal Ratnakumar
IPC分类号： G11C16/04 , G11C16/08 , H01L21/8247 , H01L29/788
CPC分类号： H01L27/11521 , G11C16/0433 , G11C16/08 , H01L27/11524
摘要： An electrically erasable programmable read only memory (EEPROM) cell including a tunnel dielectric layer formed over a semiconductor substrate. The EEPROM cell may have a floating gate transistor and a select transistor. The floating gate transistor may have a floating gate formed over the tunnel dielectric and a control gate formed over the floating gate. The select transistor may have a first gate formed over the tunnel dielectric and a second gate formed over the first gate. The second gate may be electrically connected to the first gate.
摘要翻译：一种电可擦除可编程只读存储器（EEPROM）单元，包括形成在半导体衬底上的隧道介电层。 EEPROM单元可以具有浮栅晶体管和选择晶体管。浮置栅极晶体管可以具有形成在隧道电介质上的浮动栅极和形成在浮动栅极上的控制栅极。选择晶体管可以具有形成在隧道电介质上的第一栅极和形成在第一栅极上的第二栅极。第二栅极可以电连接到第一栅极。

4. 发明授权

US06803289B1 Bipolar transistor and method for making the same 有权
标题翻译：双极晶体管及其制作方法
公开(公告)号：US06803289B1
公开(公告)日：2004-10-12
申请号：US10184697
申请日：2002-06-28
申请人： Prabhuram Gopalan , K. Nirmal Ratnakumar , Chandrasekhar R. Gorla
发明人： Prabhuram Gopalan , K. Nirmal Ratnakumar , Chandrasekhar R. Gorla
IPC分类号： H01L21331
CPC分类号： H01L29/66287 , H01L21/8249
摘要： A method for fabricating a bipolar transistor is provided. In some cases, the method may include patterning an epitaxial layer to expose one or more regions of a semiconductor topography. The method may further include depositing an intermediate layer above the exposed regions and remaining portions of the epitaxial layer. A conductive emitter structure may then be formed above and within the intermediate layer. In another embodiment, the method may include etching a first dielectric layer in alignment with a patterned base of a bipolar transistor while simultaneously etching a second dielectric layer in alignment with a patterned emitter structure of the bipolar transistor. In yet other embodiments, the method may include depositing an intermediate layer which is substantially etch resistant to a resist stripping process. In addition or alternatively, the intermediate layer may include etch characteristics that are substantially similar to a conductive layer formed above the intermediate layer.
摘要翻译：提供一种制造双极晶体管的方法。在一些情况下，该方法可以包括图案化外延层以暴露半导体形貌的一个或多个区域。该方法还可以包括在暴露区域和外延层的剩余部分之上沉积中间层。然后可以在中间层的上方和内部形成导电发射体结构。在另一个实施例中，该方法可以包括蚀刻与双极晶体管的图案化基底对准的第一介电层，同时蚀刻与双极晶体管的图案化发射极结构对准的第二介电层。在其他实施例中，该方法可以包括沉积对抗蚀剂剥离工艺基本上耐蚀刻的中间层。另外或替代地，中间层可以包括与在中间层上形成的导电层基本相似的蚀刻特性。

5. 发明授权

US5986932A Non-volatile static random access memory and methods for using same 失效
标题翻译：非易失性静态随机存取存储器及其使用方法
公开(公告)号：US5986932A
公开(公告)日：1999-11-16
申请号：US885156
申请日：1997-06-30
申请人： K. Nirmal Ratnakumar , Frederick B. Jenne
发明人： K. Nirmal Ratnakumar , Frederick B. Jenne
IPC分类号： G11C14/00 , G11C7/00
CPC分类号： G11C14/00
摘要： The state of a memory cell is stored by selectively imbalancing threshold voltages of storage elements of the memory cell. The threshold voltages may be selectively imbalanced by pulsing the supply voltage for the memory cell from an operating voltage level to a programming voltage level. This may be accomplished by raising the supply voltage from the operating voltage level to the programming voltage level for a period of time sufficient to store the state of the memory cell by monitoring the leakage current from the programming voltage level such that it just falls below a preestablished limit. Alternatively, the supply voltage may be repeatedly toggled between the operating voltage level and the programming voltage level for fixed time intervals until the state of the memory cell is stored. The number of toggling operations may be determined by monitoring the leakage current such that it just falls exceeds a predetermined limit. The programming voltage level may be approximately twice the operating voltage level or greater. Selectively imbalancing the threshold voltages of the storage elements may be accomplished by creating a first electric field within a first of the storage elements to tunnel electrons off of a floating gate of the first storage element and creating a second electric field within a second of the storage elements to inject the electrons onto a floating gate of the second storage element. Preferably, these electric fields are created simultaneously by applying the programming voltage to the memory cell.
摘要翻译：通过选择性地不平衡存储器单元的存储元件的阈值电压来存储存储器单元的状态。可以通过将存储器单元的电源电压从工作电压电平脉冲到编程电压电平来选择性地不平衡阈值电压。这可以通过将电源电压从工作电压电平提高到编程电压电平来实现，该时间段足以通过监视来自编程电压电平的漏电流来存储存储器单元的状态，使得其仅低于预设限制或者，可以在固定时间间隔之间的工作电压电平和编程电压电平之间重复地切换电源电压，直到存储单元的状态被存储。可以通过监视泄漏电流使得其刚刚下降超过预定极限来确定切换操作的数量。编程电压电平可能大约是工作电压电平的两倍或更大。选择性地平衡存储元件的阈值电压可以通过在第一存储元件内产生第一电场来实现，以将电子从第一存储元件的浮置栅极引出，并在第二存储器的第二存储器内产生第二电场用于将电子注入到第二存储元件的浮动栅极上的元件。优选地，通过将编程电压施加到存储器单元来同时产生这些电场。

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