专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5986932A Non-volatile static random access memory and methods for using same 失效
标题翻译：非易失性静态随机存取存储器及其使用方法
公开(公告)号：US5986932A
公开(公告)日：1999-11-16
申请号：US885156
申请日：1997-06-30
申请人： K. Nirmal Ratnakumar , Frederick B. Jenne
发明人： K. Nirmal Ratnakumar , Frederick B. Jenne
IPC分类号： G11C14/00 , G11C7/00
CPC分类号： G11C14/00
摘要： The state of a memory cell is stored by selectively imbalancing threshold voltages of storage elements of the memory cell. The threshold voltages may be selectively imbalanced by pulsing the supply voltage for the memory cell from an operating voltage level to a programming voltage level. This may be accomplished by raising the supply voltage from the operating voltage level to the programming voltage level for a period of time sufficient to store the state of the memory cell by monitoring the leakage current from the programming voltage level such that it just falls below a preestablished limit. Alternatively, the supply voltage may be repeatedly toggled between the operating voltage level and the programming voltage level for fixed time intervals until the state of the memory cell is stored. The number of toggling operations may be determined by monitoring the leakage current such that it just falls exceeds a predetermined limit. The programming voltage level may be approximately twice the operating voltage level or greater. Selectively imbalancing the threshold voltages of the storage elements may be accomplished by creating a first electric field within a first of the storage elements to tunnel electrons off of a floating gate of the first storage element and creating a second electric field within a second of the storage elements to inject the electrons onto a floating gate of the second storage element. Preferably, these electric fields are created simultaneously by applying the programming voltage to the memory cell.
摘要翻译：通过选择性地不平衡存储器单元的存储元件的阈值电压来存储存储器单元的状态。可以通过将存储器单元的电源电压从工作电压电平脉冲到编程电压电平来选择性地不平衡阈值电压。这可以通过将电源电压从工作电压电平提高到编程电压电平来实现，该时间段足以通过监视来自编程电压电平的漏电流来存储存储器单元的状态，使得其仅低于预设限制或者，可以在固定时间间隔之间的工作电压电平和编程电压电平之间重复地切换电源电压，直到存储单元的状态被存储。可以通过监视泄漏电流使得其刚刚下降超过预定极限来确定切换操作的数量。编程电压电平可能大约是工作电压电平的两倍或更大。选择性地平衡存储元件的阈值电压可以通过在第一存储元件内产生第一电场来实现，以将电子从第一存储元件的浮置栅极引出，并在第二存储器的第二存储器内产生第二电场用于将电子注入到第二存储元件的浮动栅极上的元件。优选地，通过将编程电压施加到存储器单元来同时产生这些电场。

2. 发明授权

US06798691B1 Asymmetric dot shape for increasing select-unselect margin in MRAM devices 有权
标题翻译：用于增加MRAM器件中选择 - 未选择余量的不对称点形状
公开(公告)号：US06798691B1
公开(公告)日：2004-09-28
申请号：US10184232
申请日：2002-06-28
申请人： Kamel Ounadjela , Frederick B. Jenne
发明人： Kamel Ounadjela , Frederick B. Jenne
IPC分类号： G11C1114
CPC分类号： G11C11/16 , H01L43/08
摘要： A magnetic memory cell and method for improving the write selectivity of memory cells in an MRAM array is provided herein. In particular, the magnetic memory cell may have a magnetic layer with a shape that is substantially asymmetrical about at least one axis of the magnetic layer. Such asymmetry may advantageously reduce and/or eliminate the effects of variations in the fabrication process. In addition, an asymmetrical memory shape may induce a relatively consistent equilibrium vector state, allowing a single switching mechanism to set the magnetic direction of the cell. Furthermore, a method is provided for programming a memory cell, in which the amount of current needed during a writing procedure is advantageously reduced relative to the amount of current needed in conventional writing procedures. In this manner, the asymmetrical memory cell and method produces a storage medium having overall power requirements less than those associated with symmetrical memory cells.
摘要翻译：本文提供了用于提高MRAM阵列中存储器单元的写入选择性的磁存储单元和方法。特别地，磁存储单元可以具有磁性层，该磁性层具有关于磁性层的至少一个轴线基本不对称的形状。这种不对称可以有利地减少和/或消除制造过程中变化的影响。另外，不对称记忆形状可以引起相对一致的平衡向量状态，允许单个切换机构设置单元的磁方向。此外，提供了一种用于编程存储器单元的方法，其中相对于常规写入过程所需的电流量，有利地减少了写入过程期间所需的电流量。以这种方式，不对称存储单元和方法产生的总体功率要求小于与对称存储单元相关联的存储介质。

3. 发明授权

US07042054B1 SONOS structure including a deuterated oxide-silicon interface and method for making the same 有权
标题翻译： SONOS结构包括氘代氧化硅界面及其制造方法
公开(公告)号：US07042054B1
公开(公告)日：2006-05-09
申请号：US10740205
申请日：2003-12-18
申请人： Krishnaswamy Ramkumar , Frederick B. Jenne
发明人： Krishnaswamy Ramkumar , Frederick B. Jenne
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L21/3003 , H01L29/513 , H01L29/518 , H01L29/792
摘要： A method for processing a semiconductor topography is provided, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across one or more interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. In some embodiments, the method may include forming a deutereated nitride layer above the SONOS structure prior to the reflow process. In addition or alternatively, the method may include forming a deutereated nitride layer within the SONOS structure prior to the reflow process. In some cases, the method may further include annealing the SONOS structure with a deutereated substance prior to forming the deutereated nitride layer. In either embodiment, a SONOS structure may be formed which includes deuterium arranged within an interface of a silicon layer and an oxide layer of the structure.
摘要翻译：提供了一种用于处理半导体形貌的方法，其包括在氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）结构的一个或多个界面上扩散氘。特别地，该方法可以包括在SONOS结构之间隔开的电介质层的回流期间扩散氘穿过SONOS结构的一个或多个界面。在一些实施方案中，该方法可以包括在回流工艺之前在SONOS结构之上形成去氢化氮化物层。另外或替代地，该方法可以包括在回流工艺之前在SONOS结构内形成一个去氢化氮化物层。在一些情况下，该方法可以进一步包括在形成去氢化氮化物层之前用缺失的物质退火SONOS结构。在任一实施例中，可以形成SONOS结构，其包括排列在硅层和该结构的氧化物层的界面内的氘。

4. 发明授权

US06921965B1 Die surface magnetic field shield 有权
标题翻译：模具表面磁场屏蔽
公开(公告)号：US06921965B1
公开(公告)日：2005-07-26
申请号：US10175628
申请日：2002-06-20
申请人： Oindrila Ray , Frederick B. Jenne
发明人： Oindrila Ray , Frederick B. Jenne
IPC分类号： G11C11/16 , H01L23/552 , H01L27/22 , H01L43/02
CPC分类号： G11C11/16 , H01L23/552 , H01L27/222 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor topography is provided which includes a magnetic field shield layer formed upon a semiconductor device. In particular, the semiconductor topography may include a ferromagnetic layer adapted to shield underlying layers from external magnetic fields. Such a ferromagnetic layer may include either ferrite and/or non-ferrite materials. In some embodiments, the semiconductor topography may include a magnetic field shield layer with a different pattern configuration than an adjacent passivation layer. Consequently, a method for processing a semiconductor topography which includes patterning a magnetic field shield layer to form openings other than bond pad openings within the semiconductor topography is provided.
摘要翻译：提供半导体形貌，其包括形成在半导体器件上的磁场屏蔽层。特别地，半导体形貌可以包括适于将下层从外部磁场屏蔽的铁磁层。这种铁磁层可以包括铁素体和/或非铁氧体材料。在一些实施例中，半导体形貌可以包括具有与相邻钝化层不同的图案配置的磁场屏蔽层。因此，提供一种处理半导体形貌的方法，其包括在半导体形貌内图形化磁场屏蔽层以形成不同于焊盘开口的开口。

5. 发明授权

US07095647B1 Magnetic memory array with an improved world line configuration 有权
标题翻译：具有改进的世界线配置的磁存储阵列
公开(公告)号：US07095647B1
公开(公告)日：2006-08-22
申请号：US10325008
申请日：2002-12-20
申请人： Frederick B. Jenne , Gary A. Gibbs
发明人： Frederick B. Jenne , Gary A. Gibbs
IPC分类号： G11C11/00
CPC分类号： G11C11/16 , G11C5/14
摘要： A magnetic memory array with an improved word line configuration is provided. In some embodiments, the magnetic memory array may be adapted to selectively supply voltage from a single source line to one or more transistors arranged within a first row of the magnetic memory array and to one or more transistors arranged within a second row of the magnetic memory array. In addition or alternatively, the magnetic memory array may be configured to enable current flow along a single current path through a magnetic junction and along multiple paths extending from the single current path to a plurality of transistors. In some embodiments, the plurality of transistors may be formed from a contiguous conductive structure comprising the word line. In some cases, the word line may be configured to include at least two transistors that share a common diffusion region.
摘要翻译：提供了具有改进的字线配置的磁存储器阵列。在一些实施例中，磁存储器阵列可以适于选择性地将电压从单个源极线提供给布置在磁存储器阵列的第一行内的一个或多个晶体管和布置在磁存储器的第二行内的一个或多个晶体管数组。另外或替代地，磁存储器阵列可以被配置为使得能够沿着通过磁结的单个电流路径沿着从单个电流路径延伸到多个晶体管的多个路径的电流流动。在一些实施例中，多个晶体管可以由包括字线的连续导电结构形成。在一些情况下，字线可以被配置为包括共享公共扩散区域的至少两个晶体管。

6. 发明授权

US07057919B1 Magnetic memory array configuration 失效
标题翻译：磁记忆阵列配置
公开(公告)号：US07057919B1
公开(公告)日：2006-06-06
申请号：US10699155
申请日：2003-10-31
申请人： Frederick B. Jenne , Gary A. Gibbs
发明人： Frederick B. Jenne , Gary A. Gibbs
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15
CPC分类号： G11C11/16
摘要： A memory array configuration is provided that includes a plurality of magnetic cell junctions and a conductive line comprising a gate of a first transistor configured to enable a read operation for one of a plurality of magnetic cell junctions and a gate of a second transistor configured to enable a write operation for another of the plurality of magnetic cell junctions. Another memory array configuration is provided which includes a set of conductive structures serially coupled to a bit line spaced apart from and, in some embodiments, directly above a magnetic cell junction, a transistor coupled to the set of conductive structures and a program line collectively configured with the bit line to induce current flow through the set of conductive structures upon an application of a voltage to a gate of the transistor. A method for operating such a magnetic memory array is also contemplated herein.
摘要翻译：提供了一种存储器阵列配置，其包括多个磁性细胞结和包括第一晶体管的栅极的导线，该第一晶体管的栅极被配置为能够对多个磁性细胞结中的一个进行读取操作，并且第二晶体管的栅极被配置为使能对多个磁性细胞结中的另一个的记录操作。提供了另一种存储器阵列配置，其包括一组导电结构，其串联耦合到与磁细胞结连接并且在一些实施例中直接位于磁性细胞结的上方的位线，耦合到该组导电结构的晶体管和共同配置的编程线利用位线来在施加电压到晶体管的栅极时感应电流流过该组导电结构。这里还考虑了用于操作这种磁存储器阵列的方法。

7. 发明授权

US06677213B1 SONOS structure including a deuterated oxide-silicon interface and method for making the same 有权
标题翻译： SONOS结构包括氘代氧化硅界面及其制造方法
公开(公告)号：US06677213B1
公开(公告)日：2004-01-13
申请号：US10094108
申请日：2002-03-08
申请人： Krishnaswamy Ramkumar , Frederick B. Jenne
发明人： Krishnaswamy Ramkumar , Frederick B. Jenne
IPC分类号： H01L21336
CPC分类号： H01L21/28176 , H01L21/28194 , H01L21/28202 , H01L21/28282 , H01L21/3003 , H01L29/513 , H01L29/518 , H01L29/792
摘要： A method for processing a semiconductor topography is provided, which includes diffusing deuterium across one or more interfaces of a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In particular, the method may include diffusing deuterium across one or more interfaces of a SONOS structure during a reflow of a dielectric layer spaced above the SONOS structure. In some embodiments, the method may include forming a deutereated nitride layer above the SONOS structure prior to the reflow process. In addition or alternatively, the method may include forming a deutereated nitride layer within the SONOS structure prior to the reflow process. In some cases, the method may further include annealing the SONOS structure with a deutereated substance prior to forming the deutereated nitride layer. In either embodiment, a SONOS structure may be formed which includes deuterium arranged within an interface of a silicon layer and an oxide layer of the structure.
摘要翻译：提供了一种用于处理半导体形貌的方法，其包括在氧化硅 - 氮化物 - 氧化物 - 硅（SONOS）结构的一个或多个界面上扩散氘。特别地，该方法可以包括在SONOS结构之间隔开的电介质层的回流期间扩散氘穿过SONOS结构的一个或多个界面。在一些实施方案中，该方法可以包括在回流工艺之前在SONOS结构之上形成去氢化氮化物层。另外或替代地，该方法可以包括在回流工艺之前在SONOS结构内形成一个去氢化氮化物层。在一些情况下，该方法可以进一步包括在形成去氢化氮化物层之前用缺失的物质退火SONOS结构。在任一实施例中，可以形成SONOS结构，其包括排列在硅层和该结构的氧化物层的界面内的氘。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式