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1. 发明授权

US5498978A Field programmable gate array 失效
标题翻译：现场可编程门阵列
公开(公告)号：US5498978A
公开(公告)日：1996-03-12
申请号：US237851
申请日：1994-05-04
申请人： Makoto Takahashi , Fumitoshi Hatori , Kazutaka Nogami , Masanori Uchida
发明人： Makoto Takahashi , Fumitoshi Hatori , Kazutaka Nogami , Masanori Uchida
IPC分类号： H01L21/82 , G11C17/16 , H01L27/118 , H03K19/173 , H03K19/177 , H01H37/76 , H03K17/687
CPC分类号： H03K19/17796 , G11C17/16 , H03K19/17704
摘要： A field programmable gate array comprises: a first wiring group composed of a plurality of first wirings (C1, C2, C3, . . . ); a second wiring group composed of a plurality of second wirings (R1, R2, R3, . . . ); a plurality of programmable elements (A11, A12, A13, . . . ) arranged into an array pattern at at least one of plural intersections between the first wirings and the second wirings, each of the programmable element being connected to each of the first wirings (C1, C2, C3, . . . ) at one end thereof and to each of the second wirings (R1, R2, R3, . . . ) at the other end thereof and being programmed by a programming voltage applied between the first wiring and second wiring to switch connection between the first and second wirings to disconnection between the two wirings or vice versa; and voltage supplying sections (CD1, RD1) for applying a programming voltage between the first and second wirings (C1, C2, C3, . . . ; R1, R2, R3, . . . ) between which the programmable element to be programmed is connected and an intermediate voltage between the first and second wirings between which the programmable element not to be programmed is connected, the intermediate voltage being lower than the programming voltage to such an extent as not to affect state of the programmable elements (A11, A12, A13, . . . ).
摘要翻译：现场可编程门阵列包括：由多个第一布线（C1，C2，C3 ...）组成的第一布线组; 由多个第二布线（R1，R2，R3 ...）组成的第二布线组; 在第一布线和第二布线之间的多个交点中的至少一个布置成阵列图案的多个可编程元件（A11，A12，A13 ...），每个可编程元件连接到每个第一布线（C1，C2，C3，...）和其另一端的每个第二布线（R1，R2，R3 ...），并通过施加在第一布线以及用于将所述第一和第二布线之间的连接切换到所述两条布线之间的断开的第二布线，反之亦然; 以及用于在第一和第二布线（C1，C2，C3，...，R1，R2，R3等）之间施加编程电压的电压供应部分（CD1，RD1），其中要编程的可编程元件所述第一和第二布线之间的中间电压被连接在可编程元件不被编程之间的中间电压，所述中间电压低于编程电压至不影响可编程元件（A11，A12， A13，...）。

2. 发明授权

US5459342A Field programmable gate array with spare circuit block 失效
标题翻译：具有备用电路块的现场可编程门阵列
公开(公告)号：US5459342A
公开(公告)日：1995-10-17
申请号：US146312
申请日：1993-11-02
申请人： Kazutaka Nogami , Takayasu Sakurai , Fumitoshi Hatori
发明人： Kazutaka Nogami , Takayasu Sakurai , Fumitoshi Hatori
IPC分类号： H01L21/82 , G06F11/20 , H01L27/118 , H03K19/173 , H01L21/70 , H01L27/00 , H03K19/177
CPC分类号： H03K19/17764
摘要： A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at least one interconnection for connecting at least one of the circuit blocks and the at least one spare circuit programmably; and at least one connecting element disposed on the interconnection of the set of interconnections which turns its status from a turned-on state to a turned-off state or vice versa when programmed. When any one of the circuit blocks is defective, since the defective circuit block can be replaced with the spare circuit block, it is possible to retain any desired functions of the logic circuits by programming the connecting means, thus improving the production yield of the field programmable gate array and thereby reducing the manufacturing cost thereof.
摘要翻译：现场可编程门阵列包括：多个具有逻辑电路的电路块; 至少一个具有逻辑电路的备用电路块; 一组互连，其包括至少一个互连，用于可编程地连接至少一个所述电路块和所述至少一个备用电路; 以及至少一个连接元件，其设置在所述一组互连件的互连上，其在编程时将其状态从打开状态转变为关闭状态，反之亦然。当任何一个电路块有缺陷时，由于可以用备用电路块代替有缺陷的电路块，可以通过编程连接装置来保持逻辑电路的所需功能，从而提高了现场的产量可编程门阵列，从而降低其制造成本。

3. 发明授权

US5764588A Memory circuit 失效
标题翻译：存储电路
公开(公告)号：US5764588A
公开(公告)日：1998-06-09
申请号：US848223
申请日：1997-04-29
申请人： Kazutaka Nogami , Fumitoshi Hatori
发明人： Kazutaka Nogami , Fumitoshi Hatori
IPC分类号： G11C11/41 , G11C7/18 , G11C8/16 , G11C5/06
CPC分类号： G11C8/16 , G11C7/18
摘要： A single-port memory or a multi-port memory with a higher density than conventional memory devices is realized, while using the same design rule, by decreasing the number of bit lines per column or port to decrease the space for wiring and the size of the entire memory. A memory circuit includes a memory cell array arranging a plurality of memory cells in a matrix, each memory cell having at least one read port; word lines each connected to memory cells aligned in a row among the memory cells of the memory cell array, and bit lines each connected to memory cells aligned in n rows (n.gtoreq.2) among the memory cells of the memory cell array. Current drivability of access transistors of memory cells sharing n bit lines are set to satisfy the relation of 1:2: . . . :2.sup.n-1. This results in decreasing the number of bit lines and the area of the memory.
摘要翻译：实现具有比常规存储器件更高密度的单端口存储器或多端口存储器，同时使用相同的设计规则，通过减少每列或端口的位线数量以减少布线空间和尺寸整个记忆存储电路包括以矩阵形式布置多个存储单元的存储单元阵列，每个存储单元具有至少一个读端口; 每个连接到存储单元阵列的存储单元中的一行排列的存储单元的字线以及与存储单元阵列的存储单元中的n行（n> / = 2）对齐的存储单元连接的位线。共享n位线的存储单元的存取晶体管的电流驱动能力设定为满足1：2：的关系。。。：2n-1。这导致位线的数量和存储器的面积减少。

4. 发明授权

US5539331A Field programmable gate array having transmission gates and semiconductor integrated circuit for programming connection of wires 失效
标题翻译：具有传输门的现场可编程门阵列和用于编程线的连接的半导体集成电路
公开(公告)号：US5539331A
公开(公告)日：1996-07-23
申请号：US237631
申请日：1994-05-04
申请人： Fumitoshi Hatori , Kazutaka Nogami , Takayasu Sakurai , Makoto Ichida
发明人： Fumitoshi Hatori , Kazutaka Nogami , Takayasu Sakurai , Makoto Ichida
IPC分类号： H03K19/177 , H01L25/00
CPC分类号： H03K19/177 , H03K19/17704
摘要： A field programmable gate array comprises: a first wire group (8) composed of a plurality of first wires; a second wire group (7) composed of a plurality of second wires; switching sections (9) provided at least one intersection between the first and second wires of the first and second wire groups (8, 7), for determining connection and disconnection between both when programmed; and a basis cell (6B) having a first transmission gate (4) turned on in response to a high gate voltage and a second transmission gate (5) turned on in response to a low gate voltage, gates of the first and second transmission gates (4, 5) being connected to each other as a common gate or being connectable to each other as a common gate by the switching sections when programmed, input and output terminals and the common gates of the first and second transmission gates (4, 5) being connected to any of the first wires of the first wire group (8), respectively. Wiring of different lengths is provided for connecting circuit elements within the field programmable gate array, with wires of a first length being more numerous than wires of a second, longer length. The quantity of wires of different lengths varies in accordance with the -2.5 power of the length of the wires.
摘要翻译：现场可编程门阵列包括：由多条第一线组成的第一线组（8）; 由多条第二线组成的第二线组（7）切换部分（9）提供了第一和第二线组（8,7）的第一和第二线之间的至少一个交点，用于在编程时确定两者之间的连接和断开; 以及响应于高栅极电压而导通的第一传输门（4）和响应于低栅极电压导通的第二传输门（5）的基站（6B），第一和第二传输门的栅极（4,5）作为公共栅极彼此连接，或者当编程的输入和输出端子和第一和第二传输门（4,5）的公共栅极时，由开关部分作为公共栅极彼此连接）分别连接到第一线组（8）的任何第一线。提供不同长度的接线用于连接现场可编程门阵列内的电路元件，第一长度的导线比第二较长长度的导线多。不同长度的电线数量根据电线长度的-2.5功率而变化。

5. 发明授权

US5748011A Output buffer circuit 失效
标题翻译：输出缓冲电路
公开(公告)号：US5748011A
公开(公告)日：1998-05-05
申请号：US701675
申请日：1996-08-22
申请人： Makoto Takahashi , Kazutaka Nogami
发明人： Makoto Takahashi , Kazutaka Nogami
IPC分类号： H03K19/0175 , H03K19/003 , H03K19/0948 , H03K19/094
CPC分类号： H03K19/00315
摘要： In the output buffer circuit, when an enable signal is inputted to deactivate the main buffer circuit (MB1) and further when a voltage higher than the first supply voltage V.sub.DD is applied to the output terminal (I/O), since the fifth P-type transistor (QP2) is turned on, the voltage at the output terminal is applied to the gate of the third P-type transistor (QP1), so that this transistor (QP1) is perfectly turned off. Therefore, it is possible to prevent unnecessary current from flowing from the output terminal (I/O) to the first supply voltage (V.sub.DD) terminal through the third P-type transistor (QP1). Further, since the sixth P-type transistor (QP4) is turned on, the voltage at the output terminal is applied to the gate of the second P-type transistor (QP6) through the sixth P-type transistor (QP4), so that this transistor (QP6) can be perfectly turned off. Therefore, it is possible to prevent unnecessary current from flowing to the first supply voltage (V.sub.DD) terminal through the first and second P-type transistors (QP5 and QP6). Further, since a voltage higher than the first supply voltage will not be applied to the gate oxide film of the second to sixth P-type transistors all formed on the same N-type substrate, it is possible to prevent the manufacturing process from being complicated.
摘要翻译：在输出缓冲电路中，当输入使能信号以使主缓冲电路（MB1）去激活时，并且当高于第一电源电压VDD的电压施加到输出端（I / O）时，由于第五P- 类型晶体管（QP2）导通，输出端子处的电压被施加到第三P型晶体管（QP1）的栅极，使得该晶体管（QP1）完全截止。因此，可以防止不必要的电流通过第三P型晶体管（QP1）从输出端子（I / O）流向第一电源电压（VDD）端子。此外，由于第六P型晶体管（QP4）导通，所以通过第六P型晶体管（QP4）将输出端子处的电压施加到第二P型晶体管（QP6）的栅极，使得该晶体管（QP6）可以完全关闭。因此，可以防止不必要的电流通过第一和第二P型晶体管（QP5和QP6）流向第一电源电压（VDD）端子。此外，由于高于第一电源电压的电压将不会施加在同一N型衬底上形成的第二至第六P型晶体管的栅极氧化膜上，所以可以防止制造工艺复杂化。

6. 发明授权

US06374281B1 Adder 失效
标题翻译：加法器
公开(公告)号：US06374281B1
公开(公告)日：2002-04-16
申请号：US09258819
申请日：1999-02-26
申请人： Shinji Kitabayashi , Kazutaka Nogami
发明人： Shinji Kitabayashi , Kazutaka Nogami
IPC分类号： G06F750
CPC分类号： G06F7/5318 , G06F7/607 , G06F2207/4818
摘要： An adder comprises: a comparator circuit 2 for comparing values of n input signals, each of which comprises 1-bit data, with first to n-th predetermined values which are different from each other; a non-volatile memory 6 having first to n+1-th word lines, m (2m≧n+1) bit lines which are provided so as to intersect the word lines, and memory cells, each of which is provided at an intersection of each of the word lines and each of the bit lines and each of which has stored 1-bit data; and a selector circuit 4 for selecting one of the n+1 word lines on the basis of n comparison results of the comparator circuit to activate the selected word line. Thus, a plurality of bits are added at high speed.
摘要翻译：加法器包括：比较器电路2，用于将每个包括1位数据的n个输入信号的值彼此不同的第一至第n个预定值进行比较; 具有第一到第n + 1个字线的非易失性存储器6，被设置为与字线相交的m（2m> = n + 1）位线，以及存储单元，每个存储单元设置在每个字线和每个位线的每个都具有存储的1位数据; 以及选择电路4，用于根据比较器电路的n个比较结果来选择n + 1个字线中的一个，以激活所选择的字线。因此，以高速添加多个位。

7. 发明授权

US4757217A Refresh operation control circuit for semiconductor device 失效
标题翻译：半导体器件的刷新操作控制电路
公开(公告)号：US4757217A
公开(公告)日：1988-07-12
申请号：US11882
申请日：1987-02-06
申请人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
发明人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
IPC分类号： G11C11/403 , G11C11/406 , H03K3/356
CPC分类号： G11C11/406
摘要： This invention provides a refresh operation control circuit for a semiconductor memory device. Two flip-flop circuits respectively temporarily hold a normal read start command signal and a refresh start command signal generated within the memory device. A normal operation/refresh operation priority determining circuit wherein 2-input logic circuits are cross-connected so that one output in each case of each of these two flip-flop circuits provides one input of the other flip-flop circuit. The priority determining circuit determines the priority of normal read operation and refresh operation in accordance with the logic level relationship of the one inputs. Either control of the start of normal read operation or control of the start of refresh operation is carried out in accordance with the output of this determination.

8. 发明授权

US5986309A Semiconductor integrated circuit apparatus having a plurality of well bias voltage supply circuits 失效
标题翻译：具有多个阱偏压电源电路的半导体集成电路装置
公开(公告)号：US5986309A
公开(公告)日：1999-11-16
申请号：US178365
申请日：1994-01-06
申请人： Yukihiro Fujimoto , Kazutaka Nogami
发明人： Yukihiro Fujimoto , Kazutaka Nogami
IPC分类号： H01L27/08 , G11C5/14 , G11C11/401 , G11C11/407 , G11C11/408 , H01L27/02 , H01L27/10 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119
CPC分类号： G11C5/146 , H01L27/0222
摘要： A semiconductor integrated circuit apparatus comprises a semiconductor substrate, a first well region formed in the upper surface of the semiconductor substrate, a first circuit formed in the first well region, first bias voltage supply functions for supplying a bias voltage to the first well region, a second well region formed in the upper surface of the semiconductor substrate such that it does not contact the first well region, a second circuit formed in the second well region, and second bias voltage supply functions for supplying a bias voltage to the second well region.
摘要翻译：半导体集成电路装置包括半导体衬底，形成在半导体衬底的上表面中的第一阱区，形成在第一阱区中的第一电路，用于向第一阱区提供偏置电压的第一偏置电压供应功能，第二阱区，形成在半导体衬底的上表面中，使得其不接触第一阱区，形成在第二阱区中的第二电路和用于向第二阱区域提供偏置电压的第二偏压供应功能。

9. 发明授权

US5379246A Semiconductor memory device having loop configuration 失效
标题翻译：具有环路结构的半导体存储器件
公开(公告)号：US5379246A
公开(公告)日：1995-01-03
申请号：US123224
申请日：1993-09-20
申请人： Kazutaka Nogami
发明人： Kazutaka Nogami
IPC分类号： G11C11/413 , G11C7/18 , G11C8/14 , G11C11/401 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/70 , G11C7/18 , G11C8/14 , Y10S257/903
摘要： A semiconductor memory device includes a plurality of memory cells each specified by selecting one of rows and one of columns, a plurality of word lines to each of which the memory cells associated with selected one of the rows are connected in a branch form, for selecting the rows, and a plurality of bit lines to each of which the memory cells associated with selected one of the columns are connected in a branch form, for selecting the columns and providing data transmission paths for the memory cells, wherein at least one wiring of the word lines and bit lines constitutes part of at least one closed circuit. Thus, even if breaking of wire occurs in part of the wiring in the manufacturing process or in use, the memory device can be prevented from becoming a defective product due to the breaking of wire. As a result, high manufacturing yield and high reliability in use can be obtained.
摘要翻译：半导体存储器件包括多个存储器单元，每个存储器单元通过选择列和列之一来指定，多个字线，其中与所选择的一行相关联的存储器单元以分支形式连接，用于选择行和多个位线，其中与所选择的一个列相关联的存储器单元以分支形式连接，用于选择列并为存储单元提供数据传输路径，其中至少一个布线字线和位线构成至少一个闭合电路的一部分。因此，即使在制造过程或使用中部分布线发生断线，也可以防止由于断线导致的存储器件成为不良品。结果，可以获得高制造成品率和高可靠性。

10. 发明授权

US5267192A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5267192A
公开(公告)日：1993-11-30
申请号：US753048
申请日：1991-08-30
申请人： Kazutaka Nogami
发明人： Kazutaka Nogami
IPC分类号： G11C11/412 , G11C13/00
CPC分类号： G11C11/412
摘要： A semiconductor memory device having a plurality of memory cells, each memory cell having two nodes, an electric potential of each node designates a stored data, comprises: a word line; a pair of bit lines; a pair of field effect transistors (FETs) connected between the word line and the nodes; a pair of diodes connected between the bit lines and the nodes; a pair of load means connected between the nodes and a first potential; and an inverter connected to the word line for driving the FETs, wherein the electrical potential of the nodes are read out by the change of the potential of the word line controlled by the inverter.
摘要翻译：一种具有多个存储单元的半导体存储器件，每个存储器单元具有两个节点，每个节点的电位指定存储的数据，包括：字线; 一对位线连接在字线和节点之间的一对场效应晶体管（FET）; 连接在位线和节点之间的一对二极管; 连接在节点和第一电位之间的一对负载装置; 以及连接到用于驱动FET的字线的反相器，其中通过由逆变器控制的字线的电位的改变来读出节点的电位。

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