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1. 发明授权

US08499229B2 Method and apparatus for reading data from flash memory 有权
标题翻译：从闪存读取数据的方法和装置
公开(公告)号：US08499229B2
公开(公告)日：2013-07-30
申请号：US11944168
申请日：2007-11-21
申请人： Frankie Roohparvar , Vishal Sarin , William Radke
发明人： Frankie Roohparvar , Vishal Sarin , William Radke
IPC分类号： H03M13/03 , G11C29/00
CPC分类号： H03M13/23 , G06F11/1068 , G11C16/26 , G11C29/04
摘要： Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can decode error correction codes (ECC).
摘要翻译：公开了与诸如包括存储器单元阵列的闪存器件的存储器件有关的方法和装置。一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。在一个实施例中，闪存单元阵列包括字线和位线。检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。例如，维特比算法可以解码纠错码（ECC）。

2. 发明申请

US20090129169A1 METHOD AND APPARATUS FOR READING DATA FROM FLASH MEMORY 有权
标题翻译：从闪存中读取数据的方法和装置
公开(公告)号：US20090129169A1
公开(公告)日：2009-05-21
申请号：US11944168
申请日：2007-11-21
申请人： Frankie Roohparvar , Vishal Sarin , William Radke
发明人： Frankie Roohparvar , Vishal Sarin , William Radke
IPC分类号： G11C16/26
CPC分类号： H03M13/23 , G06F11/1068 , G11C16/26 , G11C29/04
摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).
摘要翻译：公开了诸如涉及包括存储器单元阵列的闪速存储器件的方法和装置。一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。在一个实施例中，闪存单元阵列包括字线和位线。检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。例如，维特比算法可用于补充纠错码（ECC）。

3. 发明授权

US07872911B2 Non-volatile multilevel memory cells with data read of reference cells 有权
标题翻译：具有参考单元数据读取的非易失性多电平存储单元
公开(公告)号：US07872911B2
公开(公告)日：2011-01-18
申请号：US12504292
申请日：2009-07-16
申请人： Vishal Sarin , Jung Sheng Hoei , Frankie Roohparvar
发明人： Vishal Sarin , Jung Sheng Hoei , Frankie Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/349 , G11C2211/5634
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold voltage (Vt) level corresponding to a target state; programming at least one reference cell of a number of reference cells coupled to the selected word line to a target reference Vt level, the number of reference cells interleaved with the number of data cells; determining a reference state based on a data read of the at least one reference cell; and changing a state read from the at least one data cell based on a change of the at least one reference cell.
摘要翻译：本公开的实施例提供用于参考单元的数据读取的用于非易失性多级存储器单元数据检索的方法，设备，模块和系统。一种方法包括将耦合到所选字线的多个数据单元的至少一个数据单元编程为对应于目标状态的目标数据阈值电压（Vt）电平; 将耦合到所选字线的多个参考单元的至少一个参考单元编程为目标参考Vt电平，与数据单元数量交织的参考单元的数量; 基于所述至少一个参考单元的数据读取确定参考状态; 以及基于所述至少一个参考单元的改变来改变从所述至少一个数据单元读取的状态。

4. 发明授权

US08553461B2 Method for kink compensation in a memory 有权
公开(公告)号：US08553461B2
公开(公告)日：2013-10-08
申请号：US13585389
申请日：2012-08-14
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.

5. 发明授权

US08243521B2 Method for kink compensation in a memory 有权
标题翻译：存储器中的扭结补偿方法
公开(公告)号：US08243521B2
公开(公告)日：2012-08-14
申请号：US12631606
申请日：2009-12-04
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译：本公开涉及存储器扭结补偿。一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。在施加顺序递增的编程脉冲数之后施加接种电压。在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。

6. 发明授权

US09087600B2 Two-part programming methods 有权
标题翻译：两部分编程方法
公开(公告)号：US09087600B2
公开(公告)日：2015-07-21
申请号：US13334339
申请日：2011-12-22
申请人： Vishal Sarin , Allahyar Vahidimowlavi
发明人： Vishal Sarin , Allahyar Vahidimowlavi
IPC分类号： G11C16/34 , G11C11/56 , G11C16/10
CPC分类号： G11C11/5628 , G11C16/0408 , G11C16/0458 , G11C16/10 , G11C16/3418 , G11C16/3427 , G11C2211/562 , G11C2211/5622 , G11C2211/5642 , G11C2211/5648
摘要： Programming a memory in two parts to reduce cell disturb is disclosed. In at least one embodiment, data is programmed in two or more sequences of programming pulses with data requiring higher programming voltages programmed first. During each programming sequence, the data which is not being currently selected for programming is inhibited. Overlapping levels and/or voltage ranges can be used.
摘要翻译：公开了两部分编程存储器以减少电池干扰。在至少一个实施例中，数据以两个或更多个编程脉冲序列编程，其中首先编程需要更高编程电压的数据。在每个编程序列期间，禁止当前未选择编程的数据。可以使用重叠电平和/或电压范围。

7. 发明授权

US08787103B2 Analog-to-digital and digital-to-analog conversion window adjustment based on reference cells in a memory device 有权
标题翻译：基于存储器件中的参考单元的模数和数模转换窗口调整
公开(公告)号：US08787103B2
公开(公告)日：2014-07-22
申请号：US13187665
申请日：2011-07-21
申请人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
发明人： Vishal Sarin , Jung-Sheng Hoei , Frankie F. Roohparvar
IPC分类号： G11C7/02
CPC分类号： G11C16/06 , G11C7/16 , G11C11/5621 , G11C16/0483 , G11C27/005 , G11C2211/5634
摘要： An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limit of the conversion window. An analog voltage representing a digital bit pattern is read from a memory cell and converted to the digital bit pattern by an analog-to-digital conversion process using the conversion window as the limits for the sampling process. This scheme helps in real time tracking of the ADC window with changes in the program window of the memory array.
摘要翻译：模数转换窗口由存储在存储器件的参考存储单元中的参考电压定义。读取第一参考电压以限定转换窗口的上限，并且读取第二参考电压以定义转换窗口的下限。表示数字位模式的模拟电压从存储单元读取，并通过使用转换窗口作为采样处理的限制的模数转换处理转换为数字位模式。该方案通过存储器阵列的程序窗口的改变，有助于实时跟踪ADC窗口。

8. 发明授权

US08773912B2 Soft landing for desired program threshold voltage 有权
标题翻译：软着陆所需的程序阈值电压
公开(公告)号：US08773912B2
公开(公告)日：2014-07-08
申请号：US13547559
申请日：2012-07-12
申请人： Vishal Sarin , Frankie F. Roohparvar , Jung-Sheng Hoei , Jonathan Pabustan
发明人： Vishal Sarin , Frankie F. Roohparvar , Jung-Sheng Hoei , Jonathan Pabustan
IPC分类号： G11C16/04 , G11C11/56
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C16/3459 , G11C2211/5621
摘要： Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final threshold voltage.
摘要翻译：公开了编程存储器单元的方法。在至少一个实施例中，通过应用第一组编程脉冲来编程到初始阈值电压，以及施加第二组编程脉冲来编程到最终阈值电压来实现编程。

9. 发明授权

US08674749B2 Fast start charge pump for voltage regulators 有权
标题翻译：用于稳压器的快速启动电荷泵
公开(公告)号：US08674749B2
公开(公告)日：2014-03-18
申请号：US12726249
申请日：2010-03-17
申请人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu AAron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
发明人： Hieu Van Tran , Sang Thanh Nguyen , Anh Ly , Hung Q. Nguyen , Wingfu AAron Lau , Nasrin Jaffari , Thuan Trong Vu , Vishal Sarin , Loc B. Hoang
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/07 , H02M1/36 , H02M1/44
摘要： A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start up. Afterwards, the boost circuits are disabled to allow the charge pump to generate high voltages without boosting. The boost circuits may be successively enabled to boost the voltage. The boost circuits may be loadless. The voltage regulator may operate in an open loop and may include a resistive divider as a reference voltage for regulating the high voltage from the charge pump. The charge pump may include spread spectrum pump clocking to reduce electromagnetic inference for capacitor or inductor on-chip charge pumping.
摘要翻译：数字多电平存储器系统包括电荷泵和用于产生用于各种存储器操作的调节高电压的电压调节器。电荷泵可以包括多个升压电路，以在快速启动期间升高电荷泵的输出。之后，升压电路被禁止，使电荷泵产生高电压而不加速。升压电路可以被连续地使能以升高电压。升压电路可以是无负载的。电压调节器可以在开环中工作，并且可以包括电阻分压器作为用于调节来自电荷泵的高电压的参考电压。电荷泵可以包括扩频泵时钟，以减少用于电容器或电感器片上电荷泵浦的电磁推理。

10. 发明授权

US08611156B2 Sensing operations in a memory device 有权
标题翻译：在存储设备中检测操作
公开(公告)号：US08611156B2
公开(公告)日：2013-12-17
申请号：US13550718
申请日：2012-07-17
申请人： Jonathan Pabustan , Vishal Sarin , Dzung H. Nguyen
发明人： Jonathan Pabustan , Vishal Sarin , Dzung H. Nguyen
IPC分类号： G11C11/34
CPC分类号： G06F3/0613 , G06F3/0655 , G06F3/0679 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3454 , G11C16/3459
摘要： Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biases a word line coupled to memory cells being sensed. Target data for each memory cell is stored in a data cache associated with that particular memory cell. When it is detected that a memory cell has turned on, the translated count output associated with the count output that is indicative of the voltage level that turned on the memory cell is compared to the target data. The comparison determines the state of the memory cell.
摘要翻译：公开了感测方法，编程方法，存储器件和存储器系统。在一种用于感测的方法中，计数电路产生计数输出和转换计数输出。计数输出被转换成时变电压，该电压偏置耦合到被感测的存储器单元的字线。每个存储器单元的目标数据被存储在与该特定存储器单元相关联的数据高速缓存器中。当检测到存储器单元已经接通时，将与指示存储器单元接通的电压电平的计数输出相关联的转换计数输出与目标数据进行比较。比较确定存储单元的状态。

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