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1. 发明授权

US07872911B2 Non-volatile multilevel memory cells with data read of reference cells 有权
标题翻译：具有参考单元数据读取的非易失性多电平存储单元
公开(公告)号：US07872911B2
公开(公告)日：2011-01-18
申请号：US12504292
申请日：2009-07-16
申请人： Vishal Sarin , Jung Sheng Hoei , Frankie Roohparvar
发明人： Vishal Sarin , Jung Sheng Hoei , Frankie Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/3418 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/349 , G11C2211/5634
摘要： Embodiments of the present disclosure provide methods, devices, modules, and systems for non-volatile multilevel memory cell data retrieval with data read of reference cells. One method includes programming at least one data cell of a number of data cells coupled to a selected word line to a target data threshold voltage (Vt) level corresponding to a target state; programming at least one reference cell of a number of reference cells coupled to the selected word line to a target reference Vt level, the number of reference cells interleaved with the number of data cells; determining a reference state based on a data read of the at least one reference cell; and changing a state read from the at least one data cell based on a change of the at least one reference cell.
摘要翻译：本公开的实施例提供用于参考单元的数据读取的用于非易失性多级存储器单元数据检索的方法，设备，模块和系统。一种方法包括将耦合到所选字线的多个数据单元的至少一个数据单元编程为对应于目标状态的目标数据阈值电压（Vt）电平; 将耦合到所选字线的多个参考单元的至少一个参考单元编程为目标参考Vt电平，与数据单元数量交织的参考单元的数量; 基于所述至少一个参考单元的数据读取确定参考状态; 以及基于所述至少一个参考单元的改变来改变从所述至少一个数据单元读取的状态。

2. 发明申请

US20090129169A1 METHOD AND APPARATUS FOR READING DATA FROM FLASH MEMORY 有权
标题翻译：从闪存中读取数据的方法和装置
公开(公告)号：US20090129169A1
公开(公告)日：2009-05-21
申请号：US11944168
申请日：2007-11-21
申请人： Frankie Roohparvar , Vishal Sarin , William Radke
发明人： Frankie Roohparvar , Vishal Sarin , William Radke
IPC分类号： G11C16/26
CPC分类号： H03M13/23 , G06F11/1068 , G11C16/26 , G11C29/04
摘要： Methods and apparatus are disclosed, such as those involving a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can be used to supplement error correction codes (ECC).
摘要翻译：公开了诸如涉及包括存储器单元阵列的闪速存储器件的方法和装置。一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。在一个实施例中，闪存单元阵列包括字线和位线。检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。例如，维特比算法可用于补充纠错码（ECC）。

3. 发明授权

US08553461B2 Method for kink compensation in a memory 有权
公开(公告)号：US08553461B2
公开(公告)日：2013-10-08
申请号：US13585389
申请日：2012-08-14
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C7/00
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.

4. 发明授权

US08499229B2 Method and apparatus for reading data from flash memory 有权
标题翻译：从闪存读取数据的方法和装置
公开(公告)号：US08499229B2
公开(公告)日：2013-07-30
申请号：US11944168
申请日：2007-11-21
申请人： Frankie Roohparvar , Vishal Sarin , William Radke
发明人： Frankie Roohparvar , Vishal Sarin , William Radke
IPC分类号： H03M13/03 , G11C29/00
CPC分类号： H03M13/23 , G06F11/1068 , G11C16/26 , G11C29/04
摘要： Methods and apparatus are disclosed related to a memory device, such as a flash memory device that includes an array of memory cells. One such method includes detecting values of charges stored in selected memory cells in the memory cell array. The method also includes processing the detected values in accordance with a Viterbi algorithm so as to determine data stored in the selected memory cells. In one embodiment, the flash memory cell array includes word lines and bit lines. Detecting the values of charges includes detecting values of charges stored in a selected row of memory cells by selecting one of the word lines. The Viterbi algorithm provides correct data where inter-signal interference between the cells affects the accuracy of read data. For example, the Viterbi algorithm can decode error correction codes (ECC).
摘要翻译：公开了与诸如包括存储器单元阵列的闪存器件的存储器件有关的方法和装置。一种这样的方法包括检测存储在存储单元阵列中的选定存储单元中的电荷的值。该方法还包括根据维特比算法处理检测到的值，以便确定存储在所选存储单元中的数据。在一个实施例中，闪存单元阵列包括字线和位线。检测费用的值包括通过选择一个字线来检测存储在所选行的存储器单元中的电荷的值。维特比算法提供正确的数据，其中单元之间的信号间干扰影响读取数据的准确性。例如，维特比算法可以解码纠错码（ECC）。

5. 发明授权

US08243521B2 Method for kink compensation in a memory 有权
标题翻译：存储器中的扭结补偿方法
公开(公告)号：US08243521B2
公开(公告)日：2012-08-14
申请号：US12631606
申请日：2009-12-04
申请人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
发明人： Violante Moschiano , Frankie Roohparvar , Giovanni Santin , Vishal Sarin , Allahyar Vahidimowlavi , Tommaso Vali
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/404 , G11C11/5628 , G11C16/3404
摘要： This disclosure concerns memory kink compensation. One method embodiment includes applying a number of sequentially incrementing programming pulses to a memory cell, with the sequential programming pulses incrementing by a first programming pulse step voltage magnitude. A seeding voltage is applied after applying the number of sequentially incrementing programming pulses. A next programming pulse is applied after applying the seeding voltage, with the next programming pulse being adjusted relative to a preceding one of the sequentially incrementing programming pulses by a second programming pulse step voltage magnitude. The second programming pulse step voltage magnitude can be less than the first programming pulse step voltage magnitude.
摘要翻译：本公开涉及存储器扭结补偿。一个方法实施例包括将多个顺序递增的编程脉冲施加到存储器单元，其中顺序编程脉冲通过第一编程脉冲阶跃电压幅度递增。在施加顺序递增的编程脉冲数之后施加接种电压。在施加播种电压之后施加下一个编程脉冲，其中下一个编程脉冲相对于先前的一个顺序递增的编程脉冲通过第二编程脉冲阶跃电压幅度被调整。第二个编程脉冲阶跃电压幅度可以小于第一个编程脉冲阶跃电压幅度。

6. 发明申请

US20090257284A1 METHOD AND APPARATUS FOR IMPROVING STORAGE PERFORMANCE USING A BACKGROUND ERASE 有权
标题翻译：用于改善使用背景消除的存储性能的方法和装置
公开(公告)号：US20090257284A1
公开(公告)日：2009-10-15
申请号：US12491846
申请日：2009-06-25
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： G11C16/04 , G06F12/00 , G06F12/02
CPC分类号： G11C16/16 , G11C16/102
摘要： Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of receiving at least one erase command and at least one erasable block address for the memory device. Also included is the act of asserting a background-process-busy flag after receiving the at least one erase command and the at least one erasable block address. At least one block in the memory associated with the at least one erasable block address is erased, wherein the erasing occurs at a time delay after receiving the at least one erase command if a background enable flag is asserted. Finally, the background-process-busy flag is negated after the erasing is complete.
摘要翻译：公开了一种被配置为在存储器件中执行背景擦除的装置，方法和计算机可读介质。包括为存储器件接收至少一个擦除命令和至少一个可擦除块地址的动作。还包括在接收到至少一个擦除命令和至少一个可擦除块地址之后断言后台处理 - 忙标志的动作。与至少一个可擦除块地址相关联的存储器中的至少一个块被擦除，其中如果背景使能标志被断言，则在接收到至少一个擦除命令之后的时间延迟发生擦除。最后，擦除完成后，后台进程忙标志被否定。

7. 发明授权

US07564721B2 Method and apparatus for improving storage performance using a background erase 失效
标题翻译：使用背景擦除来提高存储性能的方法和装置
公开(公告)号：US07564721B2
公开(公告)日：2009-07-21
申请号：US11442514
申请日：2006-05-25
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/102
摘要： Disclosed are an apparatus, method, and computer readable medium configured for performing a background erase in a memory device. Included is the act of receiving at least one erase command and at least one erasable block address for the memory device. Also included is the act of asserting a background-process-busy flag after receiving the at least one erase command and the at least one erasable block address. At least one block in the memory associated with the at least one erasable block address is erased, wherein the erasing occurs at a time delay after receiving the at least one erase command if a background enable flag is asserted. Finally, the background-process-busy flag is negated after the erasing is complete.
摘要翻译：公开了一种被配置为在存储器件中执行背景擦除的装置，方法和计算机可读介质。包括为存储器件接收至少一个擦除命令和至少一个可擦除块地址的动作。还包括在接收到至少一个擦除命令和至少一个可擦除块地址之后断言后台处理 - 忙标志的动作。与至少一个可擦除块地址相关联的存储器中的至少一个块被擦除，其中如果背景使能标志被断言，则在接收到至少一个擦除命令之后的时间延迟发生擦除。最后，擦除完成后，后台进程忙标志被否定。

8. 发明授权

US07466600B2 System and method for initiating a bad block disable process in a non-volatile memory 有权
标题翻译：在非易失性存储器中启动坏块禁止进程的系统和方法
公开(公告)号：US07466600B2
公开(公告)日：2008-12-16
申请号：US11499231
申请日：2006-08-03
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： G11C7/00
CPC分类号： G11C29/883 , G11C29/88
摘要： A system and method for disabling access to individually addressable regions of an array of non-volatile memory. In response to receiving an initial valid command, a process for disabling access to the defective portions of the array of non-volatile memory is initiated in addition to executing the initial valid command. One implementation provides receiving a memory command and determining whether an indicator has been set. In response to the indicator not being set, access to defective regions of the array of non-volatile memory is disabled in addition to executing the memory command. The indicator is also set to prevent the disabling process from being performed in response to receipt of subsequent memory commands.
摘要翻译：一种用于禁止访问非易失性存储器阵列的可单独寻址的区域的系统和方法。响应于接收到初始有效命令，除了执行初始有效命令之外，还启动了禁止访问非易失性存储器阵列的缺陷部分的处理。一个实现提供接收存储器命令并确定指示符是否已被设置。响应于未设置指示符，除了执行存储器命令之外，禁止访问非易失性存储器阵列的缺陷区域。指示符还被设置为防止响应于接收到后续存储器命令而执行禁用处理。

9. 发明申请

US20080043535A1 Method and system for minimizing number of programming pulses used to program rows of non-volatile memory cells 有权
标题翻译：用于最小化用于编程非易失性存储器单元行的编程脉冲数的方法和系统
公开(公告)号：US20080043535A1
公开(公告)日：2008-02-21
申请号：US11506375
申请日：2006-08-18
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C7/16 , G11C8/10 , G11C16/3436
摘要： A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry.
摘要翻译：闪存器件以每行最小化编程期间必须施加到单元的编程脉冲数量的方式对每行中的单元进行编程。闪速存储器件包括伪通电路，该伪通电路确定已经在行中编程的多个数据子集中的每一个中的数据错误的数量。每个子集的大小对应于从存储器件耦合的读取数据位的数量，它们同时应用于错误校验和校正电路。在一行单元的迭代编程期间，伪通电路指示伪通条件以终止行的进一步编程，如果没有一个数据子集具有超过可以由错误检查和纠正电路。

10. 发明申请

US20070189099A1 POWER EFFICIENT MEMORY AND CARDS 失效
标题翻译：功率有效的内存和卡
公开(公告)号：US20070189099A1
公开(公告)日：2007-08-16
申请号：US11691817
申请日：2007-03-27
申请人： Frankie Roohparvar
发明人： Frankie Roohparvar
IPC分类号： G11C5/14
CPC分类号： G11C5/145 , G11C5/143
摘要： A memory with an internal detection mechanism to detect the presence of either an external component of an external voltage on some no connect pins, allowing a change in the configuration of the internal voltage pumps based on those detections, or which can be used as a standard device as well. The embodiments allow the system to lower its card power consumption depending upon availability of other voltage sources in the system or available components such as inductors to provide internal voltages more efficiently.
摘要翻译：具有内部检测机制的存储器，用于检测某些无连接引脚上存在外部电压的外部元件，允许基于这些检测改变内部电压泵的配置，或可用作标准设备以及。这些实施例允许系统根据系统中其他电压源的可用性或诸如电感器的可用组件来降低其卡功耗，以更有效地提供内部电压。

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