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    • 9. 发明授权
    • Non-volatile memory with multi-gear control using on-chip folding of data
    • 具有多档位控制的非易失性存储使用片上数据折叠
    • US08468294B2
    • 2013-06-18
    • US12642611
    • 2009-12-18
    • Jianmin HuangChris AvilaLee M. GavensSteven SprouseSergey Anatolievich GorobetsNeil David Hutchinson
    • Jianmin HuangChris AvilaLee M. GavensSteven SprouseSergey Anatolievich GorobetsNeil David Hutchinson
    • G06F3/06G11C11/56
    • G06F3/0608G06F3/0611G06F3/064G06F3/0679G06F12/0246G06F2212/7202G06F2212/7203G11C7/1042G11C11/5621G11C11/5628G11C16/0483G11C16/10G11C2211/5641G11C2211/5648
    • A memory system and methods of its operation are presented. The memory system includes a controller and a non-volatile memory circuit, where the non-volatile memory circuit has a first section, where data is stored in a binary format, and a second section, where data is stored in a multi-state format. The memory system receives data from the host and performs a binary write operation of the received data to the first section of the non-volatile memory circuit. The memory system subsequently folds portions of the data from the first section of the non-volatile memory to the second section of the non-volatile memory, wherein a folding operation includes reading the portions of the data from the first section rewriting it into the second section of the non-volatile memory using a multi-state programming operation. The controller determines to operate the memory system according to one of multiple modes. The modes include a first mode, where the binary write operations to the first section of the memory are interleaved with folding operations at a first rate, and a second mode, where the number of folding operations relative to the number of the binary write operations to the first section of the memory are performed at a higher than in the first mode. The memory system then operates according to determined mode. The memory system may also include a third mode, where folding operations are background operations executed when the memory system is not receiving data from the host.
    • 介绍了一种存储系统及其操作方法。 存储器系统包括控制器和非易失性存储器电路,其中非易失性存储器电路具有数据以二进制格式存储的第一部分和第二部分,其中数据以多状态格式存储 。 存储器系统从主机接收数据,并且对所述非易失性存储器电路的第一部分执行所接收数据的二进制写操作。 存储系统随后将数据的部分从非易失性存储器的第一部分折叠到非易失性存储器的第二部分,其中折叠操作包括从第一部分读取数据的部分,将数据重写成第二部分 使用多状态编程操作的非易失性存储器的一部分。 控制器根据多种模式之一确定操作存储器系统。 这些模式包括第一模式,其中对存储器的第一部分的二进制写入操作以第一速率进行折叠操作和第二模式,其中相对于二进制写入操作的数量的折叠操作的数量 存储器的第一部分在高于第一模式下执行。 然后,存储器系统根据确定的模式进行操作。 存储器系统还可以包括第三模式,其中折叠操作是当存储器系统未从主机接收数据时执行的背景操作。
    • 10. 发明申请
    • Balanced Performance for On-Chip Folding of Non-Volatile Memories
    • 非易失性存储器片上折叠的平衡性能
    • US20120311244A1
    • 2012-12-06
    • US13491879
    • 2012-06-08
    • Yichao HuangJianmin HuangGautam Ashok DusijaOleg Kragel
    • Yichao HuangJianmin HuangGautam Ashok DusijaOleg Kragel
    • G06F12/00
    • G11C16/10G11C7/1042G11C11/5628G11C16/0483G11C2211/5641
    • A non-volatile memory system receives and stores host data. As the memory system receives host data, it initially writes the data in a binary format and then subsequently performs an on-chip folding operation on the data, storing the data in a multi-state format. The memory system interleaves the phases of the folding operations so that performance is made more uniform across allocation units, where the host stores data according to allocation units. The memory system also can perform the binary and subsequent on-chip folding operations on multiple memory planes in parallel, where the controller also balances the operations so that performance is made more uniform between planes with respect to allocation units as the data is received from the host. To further maintain performance, the memory system uses a free block list having a reserve portion that is only accessible for a specified set of commands.
    • 非易失性存储器系统接收并存储主机数据。 当存储器系统接收主机数据时,它首先以二进制格式写入数据,然后对数据执行片上折叠操作,以多状态格式存储数据。 存储器系统对折叠操作的相位进行交织,使得在分配单元之间使得性能更均匀,其中主机根据分配单元存储数据。 存储器系统还可以并行地在多个存储器平面上执行二进制和随后的片上折叠操作,其中控制器还平衡操作,使得在相对于分配单元的平面之间的性能更均匀,因为从 主办。 为了进一步维持性能,内存系统使用一个空闲块列表,该列表具有一个只能用于一组指定命令的预留部分。