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1. 发明授权

US6150853A Integrated unit gain output stage 失效
标题翻译：集成单位增益输出级
公开(公告)号：US6150853A
公开(公告)日：2000-11-21
申请号：US394688
申请日：1995-02-27
申请人： Francesco Chrappan , Maurizio Nessi , Alberto Salina
发明人： Francesco Chrappan , Maurizio Nessi , Alberto Salina
IPC分类号： H03F3/20 , H02P25/034 , H03F1/32 , H03F3/30 , H03F3/347 , H03K3/00
CPC分类号： H03F3/3062 , H02P25/034 , H03F1/3217 , H03F3/3037 , H03F2203/30057 , H03F2203/30096 , H03F2203/30129
摘要： The operation of externally connected output power transistors of a class AB amplifier is controlled without employing any external sensing resistance of the output current by driving an externally connected power transistor through a level shifting buffer and employing a limiting network composed of an integrated transistor driven by the output of a signal amplifying stage and a resistance connected in series with its drain. The buffer stage shifts the level of the driving signal of the external power transistor by a value equal to the threshold voltage of the integrated transistor of the limiting network thus ensuring the turn-off of the external power transistor under quiescent conditions.
摘要翻译：通过驱动外部连接的功率晶体管通过电平移位缓冲器来控制AB类放大器的外部连接的输出功率晶体管的操作，而不采用输出电流的任何外部感测电阻，并采用由由信号放大级的输出和与其漏极串联的电阻。缓冲级将外部功率晶体管的驱动信号的电平移动到等于限制网络的集成晶体管的阈值电压的值，从而确保在静态条件下外部功率晶体管的截止。

2. 发明授权

US5909034A Electronic device for testing bonding wire integrity 失效
标题翻译：用于测试接合线完整性的电子设备
公开(公告)号：US5909034A
公开(公告)日：1999-06-01
申请号：US648990
申请日：1996-05-17
申请人： Francesco Chrappan Soldavini , Alberto Salina
发明人： Francesco Chrappan Soldavini , Alberto Salina
IPC分类号： G01R31/02 , H01L21/60 , H01L21/66 , H01L21/822 , H01L23/482 , H01L23/528 , H01L27/04 , H01L23/49
CPC分类号： H01L24/06 , H01L23/4824 , H01L23/528 , H01L24/49 , H01L2224/05554 , H01L2224/05599 , H01L2224/48091 , H01L2224/49113 , H01L24/48 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01037 , H01L2924/01074 , H01L2924/01088 , H01L2924/13091 , H01L2924/19043
摘要： A device presenting pairs of split contact pad portions, each pair of pads having multiple bonding wire, and metal connecting strips associated therewith. The end portion of the metal connecting strips being split into parallel strip segments, each connected to a respective contact pad, so as to form a plurality of parallel current paths between a node and an external contact pin connected to the node. When current is supplied along the connecting strip a voltage drop along each segment connected to a sound bonding wire is produced, but not along the segments connected to broken or non-bonded wires. By determining the existence of a voltage difference between the contact pad portions, it is possible to detect the interruption of one or more of the bonding wires.
摘要翻译：提供成对的分离接触焊盘部分的装置，每对焊盘具有多个接合线，以及与其相关联的金属连接条。金属连接条的端部被分成平行的条状段，每条连接条分别连接到相应的接触焊盘，以在节点和连接到该节点的外部接触销之间形成多个平行的电流路径。当沿着连接条提供电流时，产生沿着连接到声音接合线的每个段的电压降，但是不沿着连接到断开或非接合线的段。通过确定接触焊盘部分之间的电压差的存在，可以检测一个或多个接合线的中断。

3. 发明授权

US07844747B2 Performance tuning using encoded performance parameter information 有权
标题翻译：使用编码性能参数信息进行性能调优
公开(公告)号：US07844747B2
公开(公告)日：2010-11-30
申请号：US10164079
申请日：2002-06-05
申请人： Giorgio Pedrazzini , Sandro Cerato , Alberto Salina
发明人： Giorgio Pedrazzini , Sandro Cerato , Alberto Salina
IPC分类号： G06F13/10
CPC分类号： H02P6/34 , Y10T29/49004
摘要： A multi-chip system in which at least one of the chips includes a performance parameter encoded thereon. After system assembly, the performance parameter can be obtained by a companion chip and used to automatically or semi-automatically fine tune the companion chip to the specific parameters of the at least one chip.
摘要翻译：一种多芯片系统，其中至少一个芯片包括在其上编码的性能参数。在系统组装之后，可以通过伴随芯片获得性能参数，并用于将伴随芯片自动或半自动微调至至少一个芯片的特定参数。

4. 发明授权

US6061258A Monitoring of current in an inductive load, PWM driven through a bridge stage 有权
标题翻译：监控电感负载中的电流，PWM通过桥接级驱动
公开(公告)号：US6061258A
公开(公告)日：2000-05-09
申请号：US129674
申请日：1998-08-05
申请人： Ezio Galbiati , Alberto Salina
发明人： Ezio Galbiati , Alberto Salina
IPC分类号： G01R19/00 , H02M7/5387 , H02P6/28 , H02P25/034 , H02M3/24
CPC分类号： H02M7/53871 , H02P25/034 , H02P6/28 , H02M2001/0009 , H02M2003/1555
摘要： Monitoring of current flowing through an inductive load driven through a bridge power stage in a PWM mode, comprises sampling the signal output by a sensing amplifier with a Sample & Hold circuit including a sampling switch and a storing capacitor. The average value of the current in the load is monitored by sampling at a half way point of an active driving phase and at a half way point of a current recirculation phase by closing the switch with a synchronizing pulse that coincides with the half way points of these phases of operation. The monitoring uses a pair of complementary periodic reference signals and uses a sensing amplifier to amplify the signal existing on a current sensing resistor functionally connected in series with the load. This produces an amplified signal representative of the current in the load to be fed to an input of an error amplifier driving a power amplifier of the bridge stage. The synchronizing pulse is generated in coincidence with the peak and with the virtual zero crossing of the two reference periodic signals, out of phase from one another by 180 degrees. A two-input logic AND gate, combining the synchronizing pulse and a masking signal of a preestablished duration generated at every switching of the bridge stage may also be employed.
摘要翻译：监控流经由PWM模式通过桥式功率级驱动的感性负载的电流，包括用包括采样开关和存储电容器的采样和保持电路对感测放大器输出的信号进行采样。负载中的电流的平均值通过在有源驱动相位的中间点和当前再循环阶段的中点进行采样来监视，该闭合开关具有同步脉冲，该同步脉冲与这些操作阶段。监视使用一对互补的周期性参考信号，并使用感测放大器来放大与负载串联的电流感测电阻上存在的信号。这产生一个放大的信号，代表要馈送给驱动桥接级的功率放大器的误差放大器的输入的负载中的电流。同步脉冲与两个参考周期信号的峰值和虚拟过零点一致地产生，彼此异相180度。也可以采用组合同步脉冲和在桥接台的每次切换时产生的预先建立的持续时间的屏蔽信号的双输入逻辑与门。

5. 发明授权

US06463211B1 Calibration technique of a BEMF detector 有权
标题翻译： BEMF检测器的校准技术
公开(公告)号：US06463211B1
公开(公告)日：2002-10-08
申请号：US09693499
申请日：2000-10-20
申请人： Roberto Peritore , Alberto Salina , Andrea Merello , Lorenzo Papillo , Francesco Vavala , Gianluca Ventura
发明人： Roberto Peritore , Alberto Salina , Andrea Merello , Lorenzo Papillo , Francesco Vavala , Gianluca Ventura
IPC分类号： H02P500
CPC分类号： G11B5/5526
摘要： The present invention relates to the positioning of the read/write transducer heads of an hard disk (HD) in a designated landing zone when requested or when the electrical power is removed from the drive. In particularly it relates to the detection of the back electromotive force (BEMF) of the motor involved in the positioning of the read/write transducer heads. According to an embodiment of the present invention a BEMF detection circuit for a voice-coil motor operative to continually generate a signal proportionally to the velocity of said voice-coil motor comprises a algebraic summing node producing at its output the BEMF of the voice-coil motor and receiving: a first voltage proportional to the voltage across the voice-coil motor; a second voltage representing the product of a first multiplier factor and a voltage proportional to the current in the coil; a third voltage representing the product of a prefixed bias voltage Vref and a second multiplier factor; said third voltage is calibrated by a single calibration circuitry operative to calibrate said second multiplier factor in response to a calibration control signal, in order to cancel said second voltage.
摘要翻译：本发明涉及当请求时或当从驱动器移除电力时将硬盘（HD）的读/写换能器头定位在指定的着陆区中。特别地，其涉及在读/写换能器头的定位中涉及的电动机的反电动势（BEMF）的检测。根据本发明的实施例，用于音圈电机的BEMF检测电路可操作以连续地产生与所述音圈电动机的速度成比例的信号，包括代数求和节点，在其输出端产生音圈的BEMF 电机和接收：与音圈电机两端的电压成比例的第一电压; 代表第一乘数和与线圈中的电流成正比的电压的乘积的第二电压; 代表预置偏置电压Vref和第二乘数的乘积的第三电压; 所述第三电压由单个校准电路校准，所述单个校准电路用于响应于校准控制信号校准所述第二乘法器因数，以便消除所述第二电压。

6. 发明授权

US06184665B2 Integrated current mode PWM drive system supply voltage scaleable while retaining a high precision 有权
标题翻译：集成电流模式PWM驱动系统电源电压可缩放，同时保持高精度
公开(公告)号：US06184665B2
公开(公告)日：2001-02-06
申请号：US09174867
申请日：1998-10-19
申请人： Alberto Salina , Donatella Brambilla
发明人： Alberto Salina , Donatella Brambilla
IPC分类号： G05F140
CPC分类号： H02P25/034 , H02P7/04
摘要： In a current mode pulse width modulation (PWM) integrated drive system having an external load, a switched-capacitor amplifier and a sample & hold stage connected in cascade form a current sensing amplifier for a control loop. The current sensing amplifier overcomes resistive mismatchings, thus permitting a scaling down of the supply voltage with high precision for the integrated drive system.
摘要翻译：在具有外部负载的电流模式脉宽调制（PWM）集成驱动系统中，开关电容放大器和级联连接的采样和保持级形成用于控制回路的电流感测放大器。电流感测放大器克服了电阻失配，从而允许集成驱动系统以高精度降低电源电压。

7. 发明授权

US6023143A Mixed PWM/linear mode driving system employing two distinct output power stages 失效
标题翻译：采用两个不同输出功率级的混合PWM /线性模式驱动系统
公开(公告)号：US6023143A
公开(公告)日：2000-02-08
申请号：US109022
申请日：1998-07-01
申请人： Alberto Salina , Donatella Brambilla
发明人： Alberto Salina , Donatella Brambilla
IPC分类号： H02P7/29 , H02P7/292 , H02P7/00
CPC分类号： G11B5/5547 , H02P25/034 , H02P7/29 , H02P7/292
摘要： A mixed mode PWM/Linear driving system for at least one inductive-resistive (L-R) actuator as a function of operating conditions thereof includes a first full bridge power stage including four power switching devices arranged in pairs for being driven in phase opposition. The system also includes a pulse width modulation (PWM) converter for producing a PWM signal directly driving the first full bridge power stage during a PWM mode operating phase. A second full bridge power stage also comprises four power switching devices of different electrical characteristics from the power switching devices of the first full bridge power stage. The system further includes a pair of amplifiers connected to respective pairs of power switching devices of the second full bridge power stage for driving same in phase opposition during a linear mode operating phase. A switch is provided for switching between the PWM mode operating phase and the linear mode operating phase.
摘要翻译：作为其工作条件的函数的至少一个电感电阻（L-R）致动器的混合模式PWM /线性驱动系统包括第一全桥功率级，其包括成对布置的四个功率开关器件，用于相位驱动。该系统还包括用于在PWM模式操作阶段期间产生直接驱动第一全桥功率级的PWM信号的脉宽调制（PWM）转换器。第二全桥功率级还包括与第一全桥功率级的功率开关器件不同的电特性的四个功率开关器件。该系统还包括连接到第二全桥功率级的相应成对的功率开关装置的一对放大器，用于在线性模式操作阶段期间以相位相对的方式驱动它们。提供用于在PWM模式操作阶段和线性模式操作阶段之间切换的开关。

8. 发明授权

US4816702A CMOS logic circuit 失效
标题翻译： CMOS逻辑电路
公开(公告)号：US4816702A
公开(公告)日：1989-03-28
申请号：US130705
申请日：1987-12-09
申请人： Alberto Salina , Domenico Rossi , Claudio Diazzi
发明人： Alberto Salina , Domenico Rossi , Claudio Diazzi
IPC分类号： H03K19/0185 , H01L21/8238 , H01L27/092 , H03K3/037 , H03K3/353 , H03K3/3565 , H03K19/092 , H03K3/26 , H03K3/29 , H03K19/096
CPC分类号： H03K3/3565 , H03K3/0372
摘要： A CMOS logic circuit for sampling data coming from TTL logic circuits under frequency control by a system's clock intrinsically faster than prior art similar circuits is obtained by combining a TTL/CMOS compatibility interface inverting stage with a first stage of the sampling circuit (master or latch stage). The circuit of the invention permits elimination of two inverters and therefore reduction of data transfer delay.
摘要翻译：通过将TTL / CMOS兼容性接口反相级与采样电路的第一级（主器件或锁存器）组合，获得CMOS逻辑电路，用于通过系统时钟对频率控制下的TTL逻辑电路进行采样，本质上比现有技术类似电路更快阶段）。本发明的电路允许消除两个逆变器，从而减少数据传输延迟。

9. 发明申请

US20110032036A1 PERFORMANCE TUNING USING ENCODED PERFORMANCE PARAMETER INFORMATION 审中-公开
标题翻译：使用编码性能参数信息进行性能调谐
公开(公告)号：US20110032036A1
公开(公告)日：2011-02-10
申请号：US12908661
申请日：2010-10-20
申请人： Giorgio Pedrazzini , Sandro Cerato , Alberto Salina
发明人： Giorgio Pedrazzini , Sandro Cerato , Alberto Salina
IPC分类号： H03G3/00 , G06F12/00 , G01R31/28 , H03F1/00
CPC分类号： H02P6/34 , Y10T29/49004
摘要： A multi-chip system in which at least one of the chips includes a performance parameter encoded thereon. After system assembly, the performance parameter can be obtained by a companion chip and used to automatically or semi-automatically fine tune the companion chip to the specific parameters of the at least one chip.
摘要翻译：一种多芯片系统，其中至少一个芯片包括在其上编码的性能参数。在系统组装之后，可以通过伴随芯片获得性能参数，并用于将伴随芯片自动或半自动微调至至少一个芯片的特定参数。

10. 发明授权

US06909572B2 Disk drive system and method for operating same 有权
标题翻译：磁盘驱动器系统及其操作方法
公开(公告)号：US06909572B2
公开(公告)日：2005-06-21
申请号：US10431336
申请日：2003-05-07
申请人： Gianluca Ventura , Alberto Salina , Alessandra Schenone , Fabio Ramaioli , Luca Anostini
发明人： Gianluca Ventura , Alberto Salina , Alessandra Schenone , Fabio Ramaioli , Luca Anostini
IPC分类号： G11B5/00 , G11B5/012 , G11B5/54 , G11B5/55 , G11B21/12 , G11B21/02
CPC分类号： G11B5/012 , G11B5/54 , G11B5/553 , G11B21/12 , G11B2005/001
摘要： A disk drive system is described which includes a disk having a magnetic surface and a motor for rotating the disk, a magnetic head being movable relative to said magnetic surface. The motor generates a back electromotive force voltage having different phases and the system comprising a plurality of switches for switching the back electromotive force voltage, a control circuit to control the plurality of switches to supply the back electromotive force voltage to direct the head to a parking position. The system also comprises a comparator adapted to compare a single phase of the back electromotive force voltage with the sum of the other phases of the back electromotive force voltage. The comparator generates an output signal representative of the comparation and the system comprises a logic block controlled by the output signal of the comparator. The logic block is adapted to determine time periods and a control sequence of the switches which is associated to the time periods. The control sequence is supplied to the control circuit so that the last generates control signals to control the plurality of switches.
摘要翻译：描述了一种磁盘驱动器系统，其包括具有磁性表面的盘和用于旋转盘的马达，磁头可相对于所述磁性表面移动。电动机产生具有不同相位的反电动势电压，并且系统包括用于切换反电动势电压的多个开关，控制电路以控制多个开关以提供反电动势电压以将头引导到停车位置。该系统还包括比较器，用于将反电动势电压的单相与反电动势电压的其它相位之和进行比较。比较器产生表示比较的输出信号，并且系统包括由比较器的输出信号控制的逻辑块。逻辑块适于确定与时间段相关联的时间段和开关的控制序列。控制序列被提供给控制电路，使得最后一个产生控制信号以控制多个开关。

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