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1. 发明申请

US20100276701A1 LOW THERMAL RESISTANCE AND ROBUST CHIP-SCALE-PACKAGE (CSP), STRUCTURE AND METHOD 审中-公开
标题翻译：低耐热性和稳定的芯片尺寸封装（CSP），结构和方法
公开(公告)号：US20100276701A1
公开(公告)日：2010-11-04
申请号：US12612616
申请日：2009-11-04
申请人： François Hébert , Nikhil Kelkar
发明人： François Hébert , Nikhil Kelkar
IPC分类号： H01L29/26 , H01L21/00
CPC分类号： H01L23/3114 , H01L23/3732 , H01L29/0657 , H01L2224/0554 , H01L2224/05568 , H01L2224/0557 , H01L2224/05571 , H01L2224/05573 , H01L2224/056 , H01L2224/16 , H01L2924/00014 , H01L2924/0102 , H01L2924/10158 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A chip scale package (CSP) semiconductor device can include a semiconductor layer, circuitry on an active surface of the semiconductor layer, and a diamond layer on a back side of the semiconductor layer. The diamond layer can provide an efficient heat sink for the semiconductor layer, with a thermal conductivity which can be more than three times greater than the thermal conductivity of copper. Further, a hardness of the diamond layer (up to about 10 times stronger than silicon) can provide effective protection against damage to the exposed semiconductor layer, for example during manufacturing, handling, and use of the CSP device. Thus a thin protective diamond layer can be used, which can result in a very thin CSP package design.
摘要翻译：芯片级封装（CSP）半导体器件可以包括半导体层，半导体层的有源表面上的电路和半导体层的背面上的金刚石层。金刚石层可以为半导体层提供有效的散热器，其热导率可以比铜的热导率大三倍以上。此外，例如在CSP器件的制造，处理和使用过程中，金刚石层的硬度（比硅高达约10倍）可以提供有效的保护，以免损坏暴露的半导体层。因此，可以使用薄的保护性金刚石层，这可以导致非常薄的CSP封装设计。

2. 发明授权

US09882049B2 Self-aligned slotted accumulation-mode field effect transistor (AccuFET) structure and method 有权
公开(公告)号：US09882049B2
公开(公告)日：2018-01-30
申请号：US14507311
申请日：2014-10-06
申请人： François Hébert , Madhur Bobde , Anup Bhalla
发明人： François Hébert , Madhur Bobde , Anup Bhalla
IPC分类号： H01L29/739 , H01L29/78 , H01L29/66 , H01L29/06 , H01L21/265 , H01L29/417 , H01L29/45 , H01L29/47 , H01L29/08
CPC分类号： H01L29/7828 , H01L21/26586 , H01L29/0619 , H01L29/0623 , H01L29/0847 , H01L29/41766 , H01L29/456 , H01L29/47 , H01L29/66666 , H01L29/7806
摘要： This invention discloses a semiconductor power device disposed in a semiconductor substrate. The semiconductor power device includes trenched gates each having a stick-up gate segment extended above a top surface of the semiconductor substrate surrounded by sidewall spacers. The semiconductor power device further includes slots opened aligned with the sidewall spacers substantially parallel to the trenched gates. The stick-up gate segment further includes a cap composed of an insulation material surrounded by the sidewall spacers. A layer of barrier metal covers a top surface of the cap and over the sidewall spacers and extends above a top surface of the slots. The slots are filled with a gate material same as the gate segment for functioning as additional gate electrodes for providing a depletion layer extends toward the trenched gates whereby a drift region between the slots and the trenched gate is fully depleted at a gate-to-drain voltage Vgs=0 volt.

3. 发明授权

US09356134B2 Charged balanced devices with shielded gate trench 有权
标题翻译：带屏蔽栅极沟槽的均衡器件
公开(公告)号：US09356134B2
公开(公告)日：2016-05-31
申请号：US14312687
申请日：2014-06-24
申请人： François Hébert
发明人： François Hébert
IPC分类号： H01L21/336 , H01L29/78 , H01L29/10 , H01L29/06
CPC分类号： H01L29/7813 , H01L29/0615 , H01L29/0623 , H01L29/0634 , H01L29/0696 , H01L29/0878 , H01L29/0886 , H01L29/1095 , H01L29/41766 , H01L29/4236 , H01L29/66734
摘要： This invention discloses a semiconductor power device disposed on a semiconductor substrate includes a plurality of deep trenches with an epitaxial layer filling said deep trenches and a simultaneously grown top epitaxial layer covering areas above a top surface of said deep trenches over the semiconductor substrate. A plurality of trench MOSFET cells disposed in said top epitaxial layer with the top epitaxial layer functioning as the body region and the semiconductor substrate acting as the drain region whereby a super junction effect is achieved through charge balance between the epitaxial layer in the deep trenches and regions in the semiconductor substrate laterally adjacent to the deep trenches. Each of the trench MOSFET cells further includes a trench gate and a gate-shielding dopant region disposed below and substantially aligned with each of the trench gates for each of the trench MOSFET cells for shielding the trench gate during a voltage breakdown.
摘要翻译：本发明公开了一种设置在半导体衬底上的半导体功率器件，包括具有填充所述深沟槽的外延层的多个深沟槽和覆盖半导体衬底上的所述深沟槽的顶表面之上的区域的同时生长的顶部外延层。设置在所述顶部外延层中的多个沟槽MOSFET单元，顶部外延层用作主体区域，并且半导体衬底用作漏极区域，由此通过深沟槽中的外延层之间的电荷平衡和半导体衬底中的与深沟槽横向相邻的区域。每个沟槽MOSFET单元还包括沟槽栅极和栅极屏蔽掺杂剂区域，其设置在用于每个沟槽MOSFET单元的每个沟槽栅极的下方并基本对齐，用于在电压击穿期间屏蔽沟槽栅极。

4. 发明授权

US08703563B2 Source and body contact structure for trench-DMOS devices using polysilicon 有权
标题翻译：使用多晶硅的沟槽DMOS器件的源和体接触结构
公开(公告)号：US08703563B2
公开(公告)日：2014-04-22
申请号：US13559490
申请日：2012-07-26
申请人： François Hébert , Anup Bhalla
发明人： François Hébert , Anup Bhalla
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/086 , H01L29/0869 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734
摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物沿着源区域的侧壁和氧化物的侧壁设置。还公开了制造这种装置的方法。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

5. 发明申请

US20140004671A1 SUPER-SELF-ALIGNED TRENCH-DMOS STRUCTURE AND METHOD 有权
标题翻译：超自对准TRENCH-DMOS结构和方法
公开(公告)号：US20140004671A1
公开(公告)日：2014-01-02
申请号：US13709614
申请日：2012-12-10
申请人： François Hébert
发明人： François Hébert
IPC分类号： H01L29/66
CPC分类号： H01L29/66734 , H01L21/2257 , H01L29/04 , H01L29/0865 , H01L29/0869 , H01L29/41766 , H01L29/456 , H01L29/66727 , H01L29/7813
摘要： A body layer is formed in an epitaxial layer and a gate electrode formed in a trench in the body and epitaxial layer. A gate insulator is disposed along a sidewall of the gate electrode between the gate electrode and the source, between the gate electrode and the P-body and between the gate electrode and the epitaxial layer. A cap insulator is disposed on top of the gate electrode. A doped spacer is disposed along a sidewall of the source and a sidewall of the gate insulator. The body layer next to the polysilicon spacer is etched back below the bottom of the polysilicon spacer. Dopants are diffused from the spacer to form the source region.
摘要翻译：主体层形成在外延层中，形成在主体和外延层中的沟槽中的栅电极。栅极绝缘体沿着栅极电极的侧壁设置在栅电极和源极之间，在栅电极和P体之间以及栅电极和外延层之间。盖绝缘体设置在栅电极的顶部。掺杂间隔物沿着源极的侧壁和栅极绝缘体的侧壁设置。多晶硅间隔物旁边的主体层被蚀刻回多晶硅间隔物的底部之下。掺杂剂从间隔物扩散以形成源区。

6. 发明申请

US20120289001A1 Method for Making Solder-top Enhanced Semiconductor Device of Low Parasitic Packaging Impedance 有权
标题翻译：制造低寄生封装阻抗的焊接增强型半导体器件的方法
公开(公告)号：US20120289001A1
公开(公告)日：2012-11-15
申请号：US13560786
申请日：2012-07-27
申请人： François Hébert , Anup Bhalla , Kai Liu , Ming Sun
发明人： François Hébert , Anup Bhalla , Kai Liu , Ming Sun
IPC分类号： H01L21/60
CPC分类号： H01L24/40 , H01L23/4952 , H01L23/49562 , H01L23/64 , H01L24/29 , H01L24/33 , H01L24/37 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L24/83 , H01L2224/05624 , H01L2224/29101 , H01L2224/29111 , H01L2224/32245 , H01L2224/37011 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/40249 , H01L2224/4103 , H01L2224/45014 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L2224/48465 , H01L2224/48472 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2224/4903 , H01L2224/49051 , H01L2224/49111 , H01L2224/49171 , H01L2224/83194 , H01L2224/83801 , H01L2224/84801 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01067 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/0132 , H01L2924/0133 , H01L2924/014 , H01L2924/13091 , H01L2924/14 , H01L2924/157 , H01L2924/181 , H01L2924/19043 , H01L2924/20752 , H01L2924/20753 , H01L2924/20754 , H01L2924/20755 , H01L2924/20756 , H01L2924/20757 , H01L2924/20758 , H01L2924/20759 , H01L2924/2076 , H01L2924/30107 , H01L2924/3011 , H01L2924/00 , H01L2924/00012 , H01L2224/29099 , H01L2224/37099
摘要： A solder-top enhanced semiconductor device is proposed for packaging. The solder-top device includes a device die with a top metal layer patterned into contact zones and contact enhancement zones. At least one contact zone is electrically connected to at least one contact enhancement zone. Atop each contact enhancement zone is a solder layer for an increased composite thickness thus lowered parasitic impedance. Where the top metal material can not form a uniform good electrical bond with the solder material, the device die further includes an intermediary layer sandwiched between and forming a uniform electrical bond with the top metal layer and the solder layer. A method for making the solder-top device includes lithographically patterning the top metal layer into the contact zones and the contact enhancement zones; then forming a solder layer atop each of the contact enhancement zones using a stencil process for an increased composite thickness.
摘要翻译：提出了一种焊顶增强型半导体器件进行封装。焊料顶部器件包括具有图案化为接触区域和接触增强区域的顶部金属层的器件裸片。至少一个接触区域电连接到至少一个接触增强区域。每个接触增强区顶部都是一个焊料层，用于增加复合材料厚度，从而降低寄生阻抗。在顶部金属材料不能与焊料材料形成均匀的良好电接合的情况下，器件裸片还包括夹在中间层之间并与顶部金属层和焊料层形成均匀的电接合的中间层。制造焊料顶部器件的方法包括将顶部金属层光刻地图案化成接触区域和接触增强区域; 然后使用用于增加的复合材料厚度的模版工艺在每个接触增强区的顶部上形成焊料层。

7. 发明申请

US20120286356A1 SOURCE AND BODY CONTACT STRUCTURE FOR TRENCH-DMOS DEVICES USING POLYSILICON 有权
标题翻译：使用POLYSILICON的TRENCH-DMOS器件的源和体接触结构
公开(公告)号：US20120286356A1
公开(公告)日：2012-11-15
申请号：US13559490
申请日：2012-07-26
申请人： François Hébert , Anup Bhalla
发明人： François Hébert , Anup Bhalla
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7813 , H01L29/086 , H01L29/0869 , H01L29/41766 , H01L29/42368 , H01L29/456 , H01L29/66727 , H01L29/66734
摘要： A semiconductor device includes a gate electrode, a top source region disposed next to the gate electrode, a drain region disposed below the bottom of the gate electrode, a oxide disposed on top of the source region and the gate electrode, and a doped polysilicon spacer disposed along a sidewall of the source region and a sidewall of the oxide. Methods for manufacturing such device are also disclosed. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
摘要翻译：半导体器件包括栅极电极，设置在栅电极旁边的顶部源极区域，设置在栅极电极底部的漏极区域，设置在源极区域和栅极电极顶部的氧化物以及掺杂多晶硅间隔物沿着源区域的侧壁和氧化物的侧壁设置。还公开了制造这种装置的方法。要强调的是，该摘要被提供以符合要求抽象的规则，允许搜索者或其他读者快速确定技术公开的主题。提交它的理解是，它不会用于解释或限制权利要求的范围或含义。

8. 发明授权

US08148817B2 Multi-die DC-DC buck power converter with efficient packaging 有权
标题翻译：多芯片DC-DC降压电源转换器，具有高效的封装
公开(公告)号：US08148817B2
公开(公告)日：2012-04-03
申请号：US12889673
申请日：2010-09-24
申请人： François Hébert , Allen Chang
发明人： François Hébert , Allen Chang
IPC分类号： H01L23/34
CPC分类号： H01L23/49562 , H01L23/49575 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/16 , H01L2224/16245 , H01L2224/32145 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48472 , H01L2224/49111 , H01L2224/49171 , H01L2224/73257 , H01L2224/73265 , H01L2924/00011 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/12032 , H01L2924/12041 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/30105 , H01L2924/30107 , H01L2924/00012 , H01L2924/00 , H01L2224/32225 , H01L2224/45099 , H01L2224/05599 , H01L2224/0401
摘要： A DC-DC buck converter in multi-die package is proposed having an output inductor, a low-side Schottky diode and a high-side vertical MOSFET controlled by a power regulating controller (PRC). The multi-die package includes a first die pad with the Schottky diode placed there on side by side with the vertical MOSFET. The PRC die is attached atop the first die pad via an insulating die bond. Alternatively, the first die pad is grounded. The vertical MOSFET is a top drain N-channel FET, the substrate of Schottky diode die is its anode. The Schottky diode and the vertical MOSFET are stacked atop the first die pad. The PRC is attached atop the first die pad via a conductive die bond. The Schottky diode die can be supplied in a flip-chip configuration with cathode being its substrate. Alternatively, the Schottky diode is supplied with anode being its substrate without the flip-chip configuration.
摘要翻译：提出了具有由功率调节控制器（PRC）控制的输出电感器，低侧肖特基二极管和高侧垂直MOSFET的多管芯封装中的DC-DC降压转换器。多管芯封装包括第一管芯焊盘，肖特基二极管与垂直MOSFET并排放置在其上。 PRC管芯通过绝缘管芯接合连接在第一管芯焊盘顶上。或者，第一管芯焊盘接地。垂直MOSFET是顶漏N沟道FET，肖特基二极管管芯的基极是其阳极。肖特基二极管和垂直MOSFET堆叠在第一芯片焊盘的顶部。 PRC通过导电芯片键连接在第一裸片焊盘顶上。肖特基二极管管芯可以以倒装芯片的形式提供，阴极是其衬底。或者，肖特基二极管被提供有阳极作为其衬底而没有倒装芯片配置。

9. 发明申请

US20120064711A1 COPPER BONDING COMPATIBLE BOND PAD STRUCTURE AND METHOD 有权
标题翻译：铜结合兼容粘结板结构与方法
公开(公告)号：US20120064711A1
公开(公告)日：2012-03-15
申请号：US13298455
申请日：2011-11-17
申请人： François Hébert , Arup Bhalia
发明人： François Hébert , Arup Bhalia
IPC分类号： H01L21/768
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/04042 , H01L2224/05017 , H01L2224/05073 , H01L2224/05124 , H01L2224/05147 , H01L2224/05556 , H01L2224/05624 , H01L2224/0603 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/4807 , H01L2224/48453 , H01L2224/48463 , H01L2224/48624 , H01L2224/48724 , H01L2224/48824 , H01L2224/85201 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： A copper bonding compatible bond pad structure and associated method is disclosed. The device bond pad structure includes a buffering structure formed of regions of interconnect metal and regions of non-conductive passivation material, the buffering structure providing buffering of underlying layers and structures of the device.
摘要翻译：公开了一种铜键合兼容的键合焊盘结构及其相关方法。器件接合焊盘结构包括由互连金属的区域和非导电钝化材料的区域形成的缓冲结构，该缓冲结构为器件的下层和结构提供缓冲。

10. 发明授权

US08110472B2 High power and high temperature semiconductor power devices protected by non-uniform ballasted sources 有权
标题翻译：由不均匀的压载源保护的大功率和高温半导体功率器件
公开(公告)号：US08110472B2
公开(公告)日：2012-02-07
申请号：US13199251
申请日：2011-08-23
申请人： François Hébert , Anup Bhalla
发明人： François Hébert , Anup Bhalla
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/7802 , H01L24/05 , H01L29/0696 , H01L29/086 , H01L29/41741 , H01L29/41775 , H01L29/456 , H01L29/7803 , H01L2224/0603 , H01L2924/1305 , H01L2924/13055 , H01L2924/1306 , H01L2924/13091 , H01L2924/00
摘要： A semiconductor power device is formed on a semiconductor substrate. The semiconductor power device includes a plurality of transistor cells distributed over different areas having varying amount of ballasting resistances depending on a local thermal dissipation in each of the different areas. An exemplary embodiment has the transistor cells with a lower ballasting resistance formed near a peripheral area and the transistor cells having a higher ballasting resistance are formed near a bond pad area. Another exemplary embodiment comprises cells with a highest ballasting resistance formed in an area around a wire-bonding pad, the transistor cells having a lower resistance are formed underneath the wire-bonding pad connected to bonding wires for dissipating heat and the transistor cells having a lowest ballasting resistance are formed in an areas away from the bonding pad.
摘要翻译：半导体功率器件形成在半导体衬底上。半导体功率器件包括分布在不同区域上的多个晶体管单元，其具有取决于每个不同区域中的局部散热的不同量的镇流电阻。示例性实施例具有在周边区域附近形成的具有较低的镇流电阻的晶体管电池，并且在接合焊盘区域附近形成具有较高耐压电性的晶体管电池。另一个示例性实施例包括形成在引线焊盘周围的区域中具有最高镇流电阻的电池，具有较低电阻的晶体管单元形成在连接到用于散热的接合线的引线接合焊盘下方，并且具有最低的晶体管电池在距离接合焊盘的区域中形成耐压性。

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