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1. 发明授权

US07313675B2 Register allocation technique 失效
标题翻译：注册分配技术
公开(公告)号：US07313675B2
公开(公告)日：2007-12-25
申请号：US11155755
申请日：2005-06-16
申请人： Fernando Latorre , José González , Antonio González
发明人： Fernando Latorre , José González , Antonio González
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A technique for allocating register resources within a microprocessor. More particularly, embodiments of the invention pertain to a register allocation technique within a microprocessor for multiple-threads of instructions or groups of micro-operations (“uops”).
摘要翻译：一种用于在微处理器内分配寄存器资源的技术。更具体地，本发明的实施例涉及用于多线程指令或微操作组（“uops”）的微处理器内的寄存器分配技术。

2. 发明授权

US07434073B2 Frequency and voltage scaling architecture 有权
公开(公告)号：US07434073B2
公开(公告)日：2008-10-07
申请号：US10999786
申请日：2004-11-29
申请人： Grigorios Magklis , José González , Antonio González
发明人： Grigorios Magklis , José González , Antonio González
IPC分类号： G06F1/26
CPC分类号： G06F1/06 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/3869 , Y02D10/126 , Y02D10/172
摘要： A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

3. 发明授权

US08612698B2 Replacement policy for hot code detection 有权
标题翻译：热代码检测替代策略
公开(公告)号：US08612698B2
公开(公告)日：2013-12-17
申请号：US12263418
申请日：2008-10-31
申请人： Pedro Lopez , F. Jesús Sánchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio González
发明人： Pedro Lopez , F. Jesús Sánchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio González
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F11/3419 , G06F11/3466 , G06F2201/81 , G06F2201/88 , G06F2201/885
摘要： Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.
摘要翻译：描述与热代码检测的替换策略有关的方法和装置。在一些实施例中，可以确定存储在存储单元中的多个条目中的哪个条目将被替换。这些条目可以对应于热代码，并且可以存储对应于热代码的年龄和执行频率信息。还描述和要求保护其他实施例。

4. 发明申请

US20100005277A1 Communicating Between Multiple Threads In A Processor 失效
标题翻译：在处理器中的多个线程之间进行通信
公开(公告)号：US20100005277A1
公开(公告)日：2010-01-07
申请号：US12446930
申请日：2006-10-27
申请人： Enric Gibert , Josep M. Codina , Fernando Latorre , José Alejandro Pineiro , Pedro López , Antonio González
发明人： Enric Gibert , Josep M. Codina , Fernando Latorre , José Alejandro Pineiro , Pedro López , Antonio González
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/526
摘要： In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括在执行第二线程时访问与第一线程相关联的寄存器的方法。在一个这样的实施例中，一种方法可以包括：如果与源操作数相关联的同步指示符表示第二线程的生成器操作的不完备，则可以防止第一线程的指令从第二线程的寄存器文件访问源操作数执行线程，并且如果同步指示符指示第二线程的生成器操作的完成，则执行指令。描述和要求保护其他实施例。

5. 发明授权

US08407497B2 Frequency and voltage scaling architecture 有权
公开(公告)号：US08407497B2
公开(公告)日：2013-03-26
申请号：US12214724
申请日：2008-06-20
申请人： Grigorios Magklis , José González , Antonio González
发明人： Grigorios Magklis , José González , Antonio González
IPC分类号： G06F1/00 , G06F1/26 , G06F1/32
CPC分类号： G06F1/06 , G06F1/3203 , G06F1/324 , G06F1/3296 , G06F9/3869 , Y02D10/126 , Y02D10/172
摘要： A method and apparatus for scaling frequency and operating voltage of at least one clock domain of a microprocessor. More particularly, embodiments of the invention relate to techniques to divide a microprocessor into clock domains and control the frequency and operating voltage of each clock domain independently of the others.

6. 发明授权

US08261046B2 Access of register files of other threads using synchronization 失效
标题翻译：使用同步访问其他线程的注册文件
公开(公告)号：US08261046B2
公开(公告)日：2012-09-04
申请号：US12446930
申请日：2006-10-27
申请人： Enric Gibert , Josep M. Codina , Fernando Latorre , José Alejandro Piñeiro , Pedro López , Antonio González
发明人： Enric Gibert , Josep M. Codina , Fernando Latorre , José Alejandro Piñeiro , Pedro López , Antonio González
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/526
摘要： In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括在执行第二线程时访问与第一线程相关联的寄存器的方法。在一个这样的实施例中，一种方法可以包括：如果与源操作数相关联的同步指示符表示第二线程的生成器操作的不完备，则可以防止第一线程的指令从第二线程的寄存器文件访问源操作数执行线程，并且如果同步指示符指示第二线程的生成器操作的完成，则执行指令。描述和要求保护其他实施例。

7. 发明授权

US08190652B2 Achieving coherence between dynamically optimized code and original code 有权
标题翻译：实现动态优化代码与原始代码之间的一致性
公开(公告)号：US08190652B2
公开(公告)日：2012-05-29
申请号：US11951614
申请日：2007-12-06
申请人： Fernando Latorre , Grigorios Magklis , Enric Gibert , Josep M. Codina , Antonio González
发明人： Fernando Latorre , Grigorios Magklis , Enric Gibert , Josep M. Codina , Antonio González
IPC分类号： G06F17/30
CPC分类号： G06F12/1027 , G06F12/0875
摘要： Techniques for achieving coherence between dynamically optimized code and original code are disclosed. In an embodiment, a search is performed for a first entry for a first page containing a first code region in a first data structure. The first code is used to determine whether a first indicator in the first entry is set to a first value. The first entry is added to the first data structure, in response to failing to find the first entry in the first data structure. A second search may be performed for a second entry for the first code region in a second data structure, in response to determining that the first indicator is set to the first value. Other embodiments are also disclosed and claimed.
摘要翻译：公开了实现动态优化代码与原始代码之间的一致性的技术。在一个实施例中，针对包含第一数据结构中的第一代码区域的第一页面的第一条目执行搜索。第一个代码用于确定第一个条目中的第一个指示符是否设置为第一个值。响应于找不到第一个数据结构中的第一个条目，第一个条目被添加到第一个数据结构。响应于确定第一指示符被设置为第一值，可以针对第二数据结构中的第一代码区域的第二条目执行第二搜索。还公开并要求保护其他实施例。

8. 发明授权

US07478198B2 Multithreaded clustered microarchitecture with dynamic back-end assignment 失效
标题翻译：具有动态后端分配的多线程集群微架构
公开(公告)号：US07478198B2
公开(公告)日：2009-01-13
申请号：US10851246
申请日：2004-05-24
申请人： Fernando Latorre , Jose Gonzalez , Antonio González
发明人： Fernando Latorre , Jose Gonzalez , Antonio González
IPC分类号： G06F12/00 , G06F13/00 , G06F3/00
CPC分类号： G06F1/32 , G06F9/3836 , G06F9/3851 , G06F9/3891
摘要： A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.
摘要翻译：提出了具有动态后端分配的多线程集群微架构。处理系统可以包括多个指令高速缓存和前端单元，每个指令高速缓存和前端单元各自处理来自指令高速缓存中的相应一个的单独线程，多个后端单元和互连网络以耦合前端和后端 -end单位。方法可以包括测量后端单元的性能度量，将测量与第一值进行比较，以及根据比较重新分配或不再分配后端单元。根据本发明的实施例的计算机系统可以包括：随机存取存储器; 系统总线以及具有多个指令高速缓存的处理器，多个前端单元，每个前端单元各自处理来自所述指令高速缓存中的相应一个的各个线程; 多个后端单元; 以及耦合到所述多个前端单元和所述多个后端单元的互连网络。

9. 发明授权

US08185700B2 Enabling speculative state information in a cache coherency protocol 有权
标题翻译：在缓存一致性协议中启用推测状态信息
公开(公告)号：US08185700B2
公开(公告)日：2012-05-22
申请号：US12226793
申请日：2006-05-30
申请人： Carlos Madriles Gimeno , Carlos García Quinones , Pedro Marcuello , Jesús Sánchez , Fernando Latorre , Antonio González
发明人： Carlos Madriles Gimeno , Carlos García Quinones , Pedro Marcuello , Jesús Sánchez , Fernando Latorre , Antonio González
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F2212/507
摘要： In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在第一高速缓存中接收总线消息的方法，所述总线消息对应于由第二线程对第二高速缓存的一部分的推测性访问，并且在第一高速缓存中动态地确定是否存在线间依存关系在第二线程与相对于该部分与第一高速缓存相关联的第一线程之间。描述和要求保护其他实施例。

10. 发明授权

US08806491B2 Thread migration to improve power efficiency in a parallel processing environment 有权
标题翻译：线程迁移以提高并行处理环境中的功率效率
公开(公告)号：US08806491B2
公开(公告)日：2014-08-12
申请号：US13453904
申请日：2012-04-23
申请人： Qiong Cai , José González , Pedro Chappero Monferrer , Grigorios Magklis , Antonio González
发明人： Qiong Cai , José González , Pedro Chappero Monferrer , Grigorios Magklis , Antonio González
IPC分类号： G06F9/46 , G06F1/00
CPC分类号： G06F9/5094 , G06F1/329 , Y02D10/22 , Y02D10/24
摘要： A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.
摘要翻译：一种选择性地移动由多个处理核并行执行的多个线程中的一个或多个的方法和系统。在一个实施例中，可以将线程从执行多个处理核心中的一个移动到在多个处理核心中的另一个处理核心中执行，基于与多个线程相关联的性能特性来移动线程。在本发明的另一实施例中，可以改变多个处理核心的功率状态，以提高与执行多个线程相关联的功率效率。

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