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1. 发明申请

US20140095956A1 ENDURANCE AWARE ERROR-CORRECTING CODE (ECC) PROTECTION FOR NON-VOLATILE MEMORIES 有权
标题翻译：非易失性存储器的耐久性错误修正代码（ECC）保护
公开(公告)号：US20140095956A1
公开(公告)日：2014-04-03
申请号：US13630541
申请日：2012-09-28
申请人： Serkan Ozdemir , Qiong Cai
发明人： Serkan Ozdemir , Qiong Cai
IPC分类号： H03M13/29
CPC分类号： G11C29/42 , G06F11/1048 , H03M13/05 , H03M13/11 , H03M13/19 , H03M13/2778
摘要： Embodiments of the invention relate to endurance-aware ECC protection for memories (e.g., phase change memories). According to one embodiment, a method includes calculating first metadata for data bits and second metadata for ECC bits which protect the data bits and the first metadata. Embodiments can include one or more first metadata bits (for the data bits), and one or more second metadata bits (for the ECC bits). An additional level of ECC protection protects the second metadata. In one embodiment, the wear-reduction modifications applied to the data bits and the ECC bits are different, and can be tailored to the behavior of the bits. According to one embodiment, the endurance-aware ECC protection described herein reduces wear due to accesses to memories while addressing the complications wear-reduction mechanisms introduce to error detection and correction systems.
摘要翻译：本发明的实施例涉及用于存储器（例如，相变存储器）的耐力感知ECC保护。根据一个实施例，一种方法包括为保护数据位和第一元数据的ECC位计算数据位的第一元数据和第二元数据。实施例可以包括一个或多个第一元数据比特（用于数据比特）和一个或多个第二元数据比特（用于ECC比特）。额外的ECC保护级别可保护第二个元数据。在一个实施例中，应用于数据位和ECC位的磨损减小修改是不同的，并且可以针对位的行为进行调整。根据一个实施例，本文所述的耐力感知ECC保护减少了由于访问存储器而导致的磨损，同时解决了对错误检测和校正系统引入的磨损减少机制的并发症。

2. 发明授权

US07698512B2 Compressing address communications between processors 有权
标题翻译：压缩处理器之间的地址通信
公开(公告)号：US07698512B2
公开(公告)日：2010-04-13
申请号：US11827904
申请日：2007-07-13
申请人： Grigorios Magklis , Jose Gonzalez , Pedro Chaparro , Qiong Cai , Antonio Gonzalez
发明人： Grigorios Magklis , Jose Gonzalez , Pedro Chaparro , Qiong Cai , Antonio Gonzalez
IPC分类号： G06F12/00
CPC分类号： G06F12/084 , G06F12/0833 , Y02D10/13
摘要： In one embodiment, the present invention includes a method for determining if data of a memory request by a first agent is in a memory region represented by a region indicator of a region table of the first agent, and transmitting a compressed address for the memory request to other agents of a system if the memory region is represented by the region indicator, otherwise transmitting a full address. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种方法，用于确定由第一代理的存储器请求的数据是否在由第一代理的区域表的区域指示符表示的存储器区域中，并且发送用于存储器请求的压缩地址如果存储器区域由区域指示符表示，则传送到系统的其它代理，否则发送完整地址。描述和要求保护其他实施例。

3. 发明授权

US07665000B2 Meeting point thread characterization 有权
标题翻译：汇点线程表征
公开(公告)号：US07665000B2
公开(公告)日：2010-02-16
申请号：US11714938
申请日：2007-03-07
申请人： Antonio Gonzalez , Qiong Cai , Jose Gonzalez , Pedro Chaparro , Grigorios Magklis , Ryan Rakvic
发明人： Antonio Gonzalez , Qiong Cai , Jose Gonzalez , Pedro Chaparro , Grigorios Magklis , Ryan Rakvic
IPC分类号： G01R31/28
CPC分类号： G06F9/52 , G06F11/3404 , G06F11/3495
摘要： An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.
摘要翻译：提供了一种基于在会议点处理期间收集的信息来识别关键线程的装置。设备的一个实施例可以包括用于在确定它们已经到达会议点时选择性地更新线程的会议点计数的逻辑。该实施例还可以包括用于周期性地识别一组线程中的哪个线程是关键线程的逻辑。关键线程可能是最慢的线程，可以通过检查会议点数来确定关键性。该实施例还可以包括选择性地操纵关键线程和/或核心的可配置属性的逻辑，关键线程将在其上运行。

4. 发明授权

US09405681B2 Workload adaptive address mapping 有权
标题翻译：工作负载自适应地址映射
公开(公告)号：US09405681B2
公开(公告)日：2016-08-02
申请号：US13995469
申请日：2011-12-28
申请人： Serkan Ozdemir , Qiong Cai , Ayose J. Falcon , Nevin Hyuseinova
发明人： Serkan Ozdemir , Qiong Cai , Ayose J. Falcon , Nevin Hyuseinova
IPC分类号： G06F12/02 , G06F13/00 , G06F12/06 , G06F13/16 , G11C13/00
CPC分类号： G06F12/06 , G06F12/0292 , G06F12/0646 , G06F13/16 , G06F2212/502 , G11C13/0004
摘要： Embodiments of the invention describe an apparatus, system and method for workload adaptive address mapping. Embodiments of the invention may receive a request to initialize a system memory including a plurality of memory banks. Using a plurality of memory address mapping schemes for memory settings for the system memory, a system characterization workload is executed during the initialization of the system memory, the system characterization workload including a plurality of transactions directed towards the system memory. Embodiments of the invention may monitor target addresses of the plurality of transactions directed towards the system memory. One of the plurality of memory address mapping schemes is selected based, at least in part, on the target addresses of the plurality of transactions.
摘要翻译：本发明的实施例描述了用于工作负载自适应地址映射的装置，系统和方法。本发明的实施例可以接收初始化包括多个存储体的系统存储器的请求。使用用于系统存储器的存储器设置的多个存储器地址映射方案，在系统存储器的初始化期间执行系统表征工作负载，系统表征工作负载包括指向系统存储器的多个事务。本发明的实施例可以监视针对系统存储器的多个事务的目标地址。至少部分地基于多个事务的目标地址来选择多个存储器地址映射方案中的一个。

5. 发明申请

US20090172424A1 THREAD MIGRATION TO IMPROVE POWER EFFICIENCY IN A PARALLEL PROCESSING ENVIRONMENT 有权
标题翻译：螺旋式移动以提高平行处理环境中的功率效率
公开(公告)号：US20090172424A1
公开(公告)日：2009-07-02
申请号：US11968060
申请日：2007-12-31
申请人： Qiong Cai , Jose Gonzalez , Pedro Chaparro Monferrer , Grigorios Magklis , Antonio Gonzalez
发明人： Qiong Cai , Jose Gonzalez , Pedro Chaparro Monferrer , Grigorios Magklis , Antonio Gonzalez
IPC分类号： G06F9/30 , G06F1/26
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/329 , G06F1/3296 , G06F9/4893 , Y02D10/126 , Y02D10/172 , Y02D10/24
摘要： A method and system to selectively move one or more of a plurality threads which are executing in parallel by a plurality of processing cores. In one embodiment, a thread may be moved from executing in one of the plurality of processing cores to executing in another of the plurality of processing cores, the moving based on a performance characteristic associated with the plurality of threads. In another embodiment of the invention, a power state of the plurality of processing cores may be changed to improve a power efficiency associated with the executing of the multiple threads.
摘要翻译：一种选择性地移动由多个处理核并行执行的多个线程中的一个或多个的方法和系统。在一个实施例中，可以将线程从执行多个处理核心中的一个移动到在多个处理核心中的另一个处理核心中执行，基于与多个线程相关联的性能特性来移动线程。在本发明的另一实施例中，可以改变多个处理核心的功率状态，以提高与执行多个线程相关联的功率效率。

6. 发明申请

US20080222466A1 Meeting point thread characterization 有权
标题翻译：汇点线程表征
公开(公告)号：US20080222466A1
公开(公告)日：2008-09-11
申请号：US11714938
申请日：2007-03-07
申请人： Antonio Gonzalez , Qiong Cai , Jose Gonzalez , Pedro Chaparro , Grigorios Magklis , Ryan Rakvic
发明人： Antonio Gonzalez , Qiong Cai , Jose Gonzalez , Pedro Chaparro , Grigorios Magklis , Ryan Rakvic
IPC分类号： G01R31/28
CPC分类号： G06F9/52 , G06F11/3404 , G06F11/3495
摘要： An apparatus associated with identifying a critical thread based on information gathered during meeting point processing is provided. One embodiment of the apparatus may include logic to selectively update meeting point counts for threads upon determining that they have arrived at a meeting point. The embodiment may also include logic to periodically identify which thread in a set of threads is a critical thread. The critical thread may be the slowest thread and criticality may be determined by examining meeting point counts. The embodiment may also include logic to selectively manipulate a configurable attribute of the critical thread and/or core upon which the critical thread will run.
摘要翻译：提供了一种基于在会议点处理期间收集的信息来识别关键线程的装置。设备的一个实施例可以包括用于在确定它们已经到达会议点时选择性地更新线程的会议点计数的逻辑。该实施例还可以包括用于周期性地识别一组线程中的哪个线程是关键线程的逻辑。关键线程可能是最慢的线程，临界点可以通过检查会议点数来确定。该实施例还可以包括选择性地操纵关键线程和/或核心的可配置属性的逻辑，关键线程将在其上运行。

7. 发明授权

US08990670B2 Endurance aware error-correcting code (ECC) protection for non-volatile memories 有权
标题翻译：针对非易失性存储器的耐久性感知纠错码（ECC）保护
公开(公告)号：US08990670B2
公开(公告)日：2015-03-24
申请号：US13630541
申请日：2012-09-28
申请人： Serkan Ozdemir , Qiong Cai
发明人： Serkan Ozdemir , Qiong Cai
IPC分类号： H03M13/00 , G06F11/00 , G11C29/42 , H03M13/11
CPC分类号： G11C29/42 , G06F11/1048 , H03M13/05 , H03M13/11 , H03M13/19 , H03M13/2778
摘要： Embodiments of the invention relate to endurance-aware ECC protection for memories (e.g., phase change memories). According to one embodiment, a method includes calculating first metadata for data bits and second metadata for ECC bits which protect the data bits and the first metadata. Embodiments can include one or more first metadata bits (for the data bits), and one or more second metadata bits (for the ECC bits). An additional level of ECC protection protects the second metadata. In one embodiment, the wear-reduction modifications applied to the data bits and the ECC bits are different, and can be tailored to the behavior of the bits. According to one embodiment, the endurance-aware ECC protection described herein reduces wear due to accesses to memories while addressing the complications wear-reduction mechanisms introduce to error detection and correction systems.
摘要翻译：本发明的实施例涉及用于存储器（例如，相变存储器）的耐力感知ECC保护。根据一个实施例，一种方法包括为保护数据位和第一元数据的ECC位计算数据位的第一元数据和第二元数据。实施例可以包括一个或多个第一元数据比特（用于数据比特）和一个或多个第二元数据比特（用于ECC比特）。额外的ECC保护级别可保护第二个元数据。在一个实施例中，应用于数据位和ECC位的磨损减小修改是不同的，并且可以针对位的行为进行调整。根据一个实施例，本文所述的耐力感知ECC保护减少了由于访问存储器而导致的磨损，同时解决了对错误检测和校正系统引入的磨损减少机制的并发症。

8. 发明申请

US20140258605A1 MEMORY IMBALANCE PREDICTION BASED CACHE MANAGEMENT 有权
标题翻译：基于记忆不平等预测的缓存管理
公开(公告)号：US20140258605A1
公开(公告)日：2014-09-11
申请号：US13793674
申请日：2013-03-11
申请人： Qiong Cai , Dyer Rolan , Blas Cuesta , Ferad Zyulkyarov , Serkan Ozdemir , Marios Nicolaides
发明人： Qiong Cai , Dyer Rolan , Blas Cuesta , Ferad Zyulkyarov , Serkan Ozdemir , Marios Nicolaides
IPC分类号： G06F12/12
CPC分类号： G06F12/12 , G06F12/122 , G06F2212/7211
摘要： Embodiments of methods, apparatuses, and storage media for memory imbalance prediction-based cache memory management are disclosed herein. In one instance, the apparatus may include a memory controller associated with a memory having a plurality of storage units. The memory controller may include logic configured to determine whether the memory enters into an imbalance state based at least in part on a difference in numbers of pending access requests to different storage units, and cause an adjustment of replacement management of a cache memory, based at least in part on a result of the determination. Other embodiments may be described and/or claimed.
摘要翻译：本文公开了用于基于存储器不平衡预测的高速缓冲存储器管理的方法，装置和存储介质的实施例。在一种情况下，该装置可以包括与具有多个存储单元的存储器相关联的存储器控制器。存储器控制器可以包括逻辑，其被配置为至少部分地基于对不同存储单元的未决访问请求的数量的差异来确定存储器是否进入不平衡状态，并且基于以下原因来调整高速缓冲存储器的替换管理至少部分取决于决定的结果。可以描述和/或要求保护其他实施例。

9. 发明申请

US20140201495A1 PAGE MISS HANDLER INCLUDING WEAR LEVELING LOGIC 有权
标题翻译： PAGE MISS HANDLER包括磨损级别逻辑
公开(公告)号：US20140201495A1
公开(公告)日：2014-07-17
申请号：US13995464
申请日：2011-12-23
申请人： Nevin Hyuseinova , Qiong Cai
发明人： Nevin Hyuseinova , Qiong Cai
IPC分类号： G06F12/10 , G06F12/02
CPC分类号： G06F12/1027 , G06F12/0246 , G06F12/1009 , G06F2212/202 , G06F2212/7211 , G11C16/3495
摘要： Embodiments of the invention describe an apparatus, system and method for utilizing a page miss handler having wear leveling logic/modules for memory devices. Embodiments of the invention may track an amount of writes directed towards cells of a memory device, and determine whether a linear address specified by a system write transaction is included in a translation-lookaside buffer (TLB). In response to determining the linear address is not included in the TLB, resulting in a TLB miss, embodiments of the invention may perform a page table walk to obtain a corresponding physical address, and convert the physical address to a device address for accessing the memory device based the tracked amount of writes. Thus, embodiments of the invention are more efficient compared to prior art solutions, as instead of all memory operations, only those that miss in the TLB incur additional wear leveling address translation overhead.
摘要翻译：本发明的实施例描述了一种用于利用具有用于存储器件的磨损均衡逻辑/模块的页面未命中处理器的装置，系统和方法。本发明的实施例可以跟踪针对存储器设备的单元的写入量，并且确定由系统写入事务指定的线性地址是否包括在翻译后备缓冲器（TLB）中。响应于确定线性地址不包括在TLB中，导致TLB未命中，本发明的实施例可以执行页表移动以获得对应的物理地址，并将物理地址转换为用于访问存储器的设备地址设备基于跟踪的写入量。因此，与现有技术的解决方案相比，本发明的实施例更有效，而不是所有存储器操作，只有那些在TLB中错过的那些才能产生额外的损耗均衡地址转换开销。

10. 发明申请

US20140095766A1 PERSISTENT LOG OPERATIONS FOR NON-VOLATILE MEMORY 有权
标题翻译：不挥发性记录的不间断日志操作
公开(公告)号：US20140095766A1
公开(公告)日：2014-04-03
申请号：US13630548
申请日：2012-09-28
申请人： Ferad Zyulkyarov , Qiong Cai
发明人： Ferad Zyulkyarov , Qiong Cai
IPC分类号： G06F12/02
CPC分类号： G06F9/467 , G06F11/141 , G06F11/1441 , G06F11/1471 , G06F11/1474 , G06F12/0246 , G06F2212/72
摘要： In an embodiment, a first delayed persistence operation to store information in a log contained in a non-volatile memory (NVM) may be performed. The information may include, for example, a current value of a variable contained in the NVM. A second delayed persistence operation to store information in the variable may be performed. A third delayed persistence operation to store information in the NVM that indicates the log is cleared may be performed. A flush operation may be performed, for example after the first, second, and third delayed persistence operations. The flush operation may commit information associated with at least one of the first, second, or third delayed persistence operations to the NVM.
摘要翻译：在一个实施例中，可以执行用于将信息存储在包含在非易失性存储器（NVM）中的日志中的第一延迟持续操作。该信息可以包括例如NVM中包含的变量的当前值。可以执行用于将信息存储在变量中的第二延迟持续操作。可以执行用于存储指示日志被清除的NVM中的信息的第三延迟持久性操作。可以执行刷新操作，例如在第一，第二和第三延迟持续操作之后。刷新操作可以将与第一，第二或第三延迟持久性操作中的至少一个相关联的信息提交给NVM。

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