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1. 发明授权

US07478198B2 Multithreaded clustered microarchitecture with dynamic back-end assignment 失效
标题翻译：具有动态后端分配的多线程集群微架构
公开(公告)号：US07478198B2
公开(公告)日：2009-01-13
申请号：US10851246
申请日：2004-05-24
申请人： Fernando Latorre , Jose Gonzalez , Antonio González
发明人： Fernando Latorre , Jose Gonzalez , Antonio González
IPC分类号： G06F12/00 , G06F13/00 , G06F3/00
CPC分类号： G06F1/32 , G06F9/3836 , G06F9/3851 , G06F9/3891
摘要： A multithreaded clustered microarchitecture with dynamic back-end assignment is presented. A processing system may include a plurality of instruction caches and front-end units each to process an individual thread from a corresponding one of the instruction caches, a plurality of back-end units, and an interconnect network to couple the front-end and back-end units. A method may include measuring a performance metric of a back-end unit, comparing the measurement to a first value, and reassigning, or not, the back-end unit according to the comparison. Computer systems according to embodiments of the invention may include: a random access memory; a system bus; and a processor having a plurality of instruction caches, a plurality of front-end units each to process an individual thread from a corresponding one of the instruction caches; a plurality of back-end units; and an interconnect network coupled to the plurality of front-end units and the plurality of back-end units.
摘要翻译：提出了具有动态后端分配的多线程集群微架构。处理系统可以包括多个指令高速缓存和前端单元，每个指令高速缓存和前端单元各自处理来自指令高速缓存中的相应一个的单独线程，多个后端单元和互连网络以耦合前端和后端 -end单位。方法可以包括测量后端单元的性能度量，将测量与第一值进行比较，以及根据比较重新分配或不再分配后端单元。根据本发明的实施例的计算机系统可以包括：随机存取存储器; 系统总线以及具有多个指令高速缓存的处理器，多个前端单元，每个前端单元各自处理来自所述指令高速缓存中的相应一个的各个线程; 多个后端单元; 以及耦合到所述多个前端单元和所述多个后端单元的互连网络。

2. 发明授权

US07313675B2 Register allocation technique 失效
标题翻译：注册分配技术
公开(公告)号：US07313675B2
公开(公告)日：2007-12-25
申请号：US11155755
申请日：2005-06-16
申请人： Fernando Latorre , José González , Antonio González
发明人： Fernando Latorre , José González , Antonio González
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A technique for allocating register resources within a microprocessor. More particularly, embodiments of the invention pertain to a register allocation technique within a microprocessor for multiple-threads of instructions or groups of micro-operations (“uops”).
摘要翻译：一种用于在微处理器内分配寄存器资源的技术。更具体地，本发明的实施例涉及用于多线程指令或微操作组（“uops”）的微处理器内的寄存器分配技术。

3. 发明授权

US08612698B2 Replacement policy for hot code detection 有权
标题翻译：热代码检测替代策略
公开(公告)号：US08612698B2
公开(公告)日：2013-12-17
申请号：US12263418
申请日：2008-10-31
申请人： Pedro Lopez , F. Jesús Sánchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio González
发明人： Pedro Lopez , F. Jesús Sánchez , Josep M. Codina , Enric Gibert , Fernando Latorre , Grigorios Magklis , Pedro Marcuello , Antonio González
IPC分类号： G06F13/00 , G06F13/28
CPC分类号： G06F11/3419 , G06F11/3466 , G06F2201/81 , G06F2201/88 , G06F2201/885
摘要： Methods and apparatus relating to a replacement policy for hot code detection are described. In some embodiments, it may be determined which entry amongst a plurality of entries stored in storage unit is to be replaced next. The entries may correspond to hot code and may store age and execution frequency information corresponding to the hot code. Other embodiments are also described and claimed.
摘要翻译：描述与热代码检测的替换策略有关的方法和装置。在一些实施例中，可以确定存储在存储单元中的多个条目中的哪个条目将被替换。这些条目可以对应于热代码，并且可以存储对应于热代码的年龄和执行频率信息。还描述和要求保护其他实施例。

4. 发明申请

US20100005277A1 Communicating Between Multiple Threads In A Processor 失效
标题翻译：在处理器中的多个线程之间进行通信
公开(公告)号：US20100005277A1
公开(公告)日：2010-01-07
申请号：US12446930
申请日：2006-10-27
申请人： Enric Gibert , Josep M. Codina , Fernando Latorre , José Alejandro Pineiro , Pedro López , Antonio González
发明人： Enric Gibert , Josep M. Codina , Fernando Latorre , José Alejandro Pineiro , Pedro López , Antonio González
IPC分类号： G06F9/44 , G06F9/46
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/526
摘要： In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括在执行第二线程时访问与第一线程相关联的寄存器的方法。在一个这样的实施例中，一种方法可以包括：如果与源操作数相关联的同步指示符表示第二线程的生成器操作的不完备，则可以防止第一线程的指令从第二线程的寄存器文件访问源操作数执行线程，并且如果同步指示符指示第二线程的生成器操作的完成，则执行指令。描述和要求保护其他实施例。

5. 发明授权

US08261046B2 Access of register files of other threads using synchronization 失效
标题翻译：使用同步访问其他线程的注册文件
公开(公告)号：US08261046B2
公开(公告)日：2012-09-04
申请号：US12446930
申请日：2006-10-27
申请人： Enric Gibert , Josep M. Codina , Fernando Latorre , José Alejandro Piñeiro , Pedro López , Antonio González
发明人： Enric Gibert , Josep M. Codina , Fernando Latorre , José Alejandro Piñeiro , Pedro López , Antonio González
IPC分类号： G06F9/30
CPC分类号： G06F9/3851 , G06F9/3838 , G06F9/526
摘要： In one embodiment, the present invention includes a method for accessing registers associated with a first thread while executing a second thread. In one such embodiment a method may include preventing an instruction of a first thread that is to access a source operand from a register file of a second thread from executing if a synchronization indicator associated with the source operand indicates incompletion of a producer operation of the second thread, and executing the instruction if the synchronization indicator indicates completion of the producer operation of the second thread. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括在执行第二线程时访问与第一线程相关联的寄存器的方法。在一个这样的实施例中，一种方法可以包括：如果与源操作数相关联的同步指示符表示第二线程的生成器操作的不完备，则可以防止第一线程的指令从第二线程的寄存器文件访问源操作数执行线程，并且如果同步指示符指示第二线程的生成器操作的完成，则执行指令。描述和要求保护其他实施例。

6. 发明授权

US08190652B2 Achieving coherence between dynamically optimized code and original code 有权
标题翻译：实现动态优化代码与原始代码之间的一致性
公开(公告)号：US08190652B2
公开(公告)日：2012-05-29
申请号：US11951614
申请日：2007-12-06
申请人： Fernando Latorre , Grigorios Magklis , Enric Gibert , Josep M. Codina , Antonio González
发明人： Fernando Latorre , Grigorios Magklis , Enric Gibert , Josep M. Codina , Antonio González
IPC分类号： G06F17/30
CPC分类号： G06F12/1027 , G06F12/0875
摘要： Techniques for achieving coherence between dynamically optimized code and original code are disclosed. In an embodiment, a search is performed for a first entry for a first page containing a first code region in a first data structure. The first code is used to determine whether a first indicator in the first entry is set to a first value. The first entry is added to the first data structure, in response to failing to find the first entry in the first data structure. A second search may be performed for a second entry for the first code region in a second data structure, in response to determining that the first indicator is set to the first value. Other embodiments are also disclosed and claimed.
摘要翻译：公开了实现动态优化代码与原始代码之间的一致性的技术。在一个实施例中，针对包含第一数据结构中的第一代码区域的第一页面的第一条目执行搜索。第一个代码用于确定第一个条目中的第一个指示符是否设置为第一个值。响应于找不到第一个数据结构中的第一个条目，第一个条目被添加到第一个数据结构。响应于确定第一指示符被设置为第一值，可以针对第二数据结构中的第一代码区域的第二条目执行第二搜索。还公开并要求保护其他实施例。

7. 发明授权

US08185700B2 Enabling speculative state information in a cache coherency protocol 有权
标题翻译：在缓存一致性协议中启用推测状态信息
公开(公告)号：US08185700B2
公开(公告)日：2012-05-22
申请号：US12226793
申请日：2006-05-30
申请人： Carlos Madriles Gimeno , Carlos García Quinones , Pedro Marcuello , Jesús Sánchez , Fernando Latorre , Antonio González
发明人： Carlos Madriles Gimeno , Carlos García Quinones , Pedro Marcuello , Jesús Sánchez , Fernando Latorre , Antonio González
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F2212/507
摘要： In one embodiment, the present invention includes a method for receiving a bus message in a first cache corresponding to a speculative access to a portion of a second cache by a second thread, and dynamically determining in the first cache if an inter-thread dependency exists between the second thread and a first thread associated with the first cache with respect to the portion. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于在第一高速缓存中接收总线消息的方法，所述总线消息对应于由第二线程对第二高速缓存的一部分的推测性访问，并且在第一高速缓存中动态地确定是否存在线间依存关系在第二线程与相对于该部分与第一高速缓存相关联的第一线程之间。描述和要求保护其他实施例。

8. 发明授权

US08477558B2 Memory apparatuses with low supply voltages 有权
标题翻译：具有低电源电压的存储设备
公开(公告)号：US08477558B2
公开(公告)日：2013-07-02
申请号：US12262070
申请日：2008-10-30
申请人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio González
发明人： Jaume Abella , Xavier Vera , Javier Carretero Casado , Pedro Chaparro Monferrer , Antonio González
IPC分类号： G11C8/00
CPC分类号： G06F13/4234 , G06F12/0802 , Y02D10/13 , Y02D10/14 , Y02D10/151
摘要： Low supply voltage memory apparatuses are presented. In one embodiment, a memory apparatus comprises a memory and a memory controller. The memory controller includes a read controller. The read controller prevents a read operation to a memory location from being completed, for at least N clock cycles after a write operation to the memory location, where N is the number of clock cycles for the memory location to stabilize after the write operation.
摘要翻译：提供了低电压存储装置。在一个实施例中，存储器装置包括存储器和存储器控制器。存储器控制器包括读控制器。读取控制器防止对存储器位置的读取操作在对存储器位置的写入操作之后至少N个时钟周期完成，其中N是在写入操作之后存储器位置稳定的时钟周期数。

9. 发明授权

US08352812B2 Protecting data storage structures from intermittent errors 有权
标题翻译：保护数据存储结构免受间歇性错误的影响
公开(公告)号：US08352812B2
公开(公告)日：2013-01-08
申请号：US11833765
申请日：2007-08-03
申请人： Xavier Vera , Jaume Abella , Javier Carretero Casado , Antonio González
发明人： Xavier Vera , Jaume Abella , Javier Carretero Casado , Antonio González
IPC分类号： G11C29/00
CPC分类号： G06F11/1008 , G06F11/1405
摘要： Embodiments of apparatuses and methods for protecting data storage structures from intermittent errors are disclosed. In one embodiment, an apparatus includes a plurality of data storage locations, execution logic, error detection logic, and control logic. The execution logic is to execute an instruction to generate a data value to store in one of the data storage locations. The error detection logic is to detect an error in the data value stored in the data storage location. The control logic is to respond to the detection of the error by causing the execution logic to re-execute the instruction to regenerate the data value to store in the data storage location, causing the error detection logic to check the data value read from the data storage location, and deactivating the data storage location if another error is detected.
摘要翻译：公开了用于保护数据存储结构免于间歇性错误的装置和方法的实施例。在一个实施例中，装置包括多个数据存储位置，执行逻辑，错误检测逻辑和控制逻辑。执行逻辑是执行指令以生成数据值以存储在数据存储位置之一中。错误检测逻辑是检测数据存储位置中存储的数据值中的错误。控制逻辑是通过使执行逻辑重新执行用于重新生成数据值以存储在数据存储位置的指令来响应错误的检测，使得错误检测逻辑检查从数据读取的数据值存储位置，如果检测到另一个错误，则停用数据存储位置。

10. 发明授权

US08402310B2 Detecting soft errors via selective re-execution 有权
标题翻译：通过选择性重新执行检测软错误
公开(公告)号：US08402310B2
公开(公告)日：2013-03-19
申请号：US13284086
申请日：2011-10-28
申请人： Xavier Vera , Oguz Ergin , Osman Unsal , Jaume Abella , Antonio González
发明人： Xavier Vera , Oguz Ergin , Osman Unsal , Jaume Abella , Antonio González
IPC分类号： G06F11/00 , G06F11/14
CPC分类号： G06F11/008 , G06F11/1497
摘要： In one embodiment, the present invention includes a method for determining a vulnerability level for an instruction executed in a processor, and re-executing the instruction if the vulnerability level is above a threshold. The vulnerability level may correspond to a soft error likelihood for the instruction while the instruction is in the processor. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于确定在处理器中执行的指令的漏洞级别的方法，以及如果漏洞级别高于阈值则重新执行该指令。漏洞级别可能对应于指令在处理器中时指令的软错误可能性。描述和要求保护其他实施例。

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