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1. 发明申请

US20050145952A1 Transistor having vertical junction edge and method of manufacturing the same 有权
标题翻译：具有垂直接合边缘的晶体管及其制造方法
公开(公告)号：US20050145952A1
公开(公告)日：2005-07-07
申请号：US10751141
申请日：2003-12-31
申请人： Fernando Gonzalez , Chandra Mouli
发明人： Fernando Gonzalez , Chandra Mouli
IPC分类号： H01L21/225 , H01L21/336 , H01L21/8234 , H01L21/8238 , H01L29/76 , H01L29/78
CPC分类号： H01L29/66636 , H01L21/2257 , H01L21/823481 , H01L21/823864 , H01L21/823878 , H01L29/41783 , H01L29/7834
摘要： Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a heavily doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the heavily doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.
摘要翻译：用于形成诸如晶体管的器件的技术具有垂直的接合边缘。更具体地说，在沟槽中形成浅沟槽并填充氧化物。可以在氧化物中形成空穴，并填充有导电材料，例如重掺杂多晶硅。在沟槽边缘处，在多晶硅和暴露的衬底之间形成垂直结，使得在热循环期间，重掺杂多晶硅将掺杂元素扩散到相邻的单晶硅中，有利地形成具有期望特性的二极管延伸。

2. 发明授权

US06693313B2 Field effect transistors, field effect transistor assemblies, and integrated circuitry 有权
标题翻译：场效应晶体管，场效应晶体管组件和集成电路
公开(公告)号：US06693313B2
公开(公告)日：2004-02-17
申请号：US10300153
申请日：2002-11-19
申请人： Fernando Gonzalez , Chandra Mouli
发明人： Fernando Gonzalez , Chandra Mouli
IPC分类号： H01L2972
CPC分类号： H01L21/28194 , H01L21/28044 , H01L21/28088 , H01L21/28114 , H01L21/28176 , H01L21/28202 , H01L21/28247 , H01L21/82345 , H01L21/823842 , H01L29/42372 , H01L29/4925 , H01L29/4941 , H01L29/4966 , H01L29/517 , H01L29/518 , Y10S257/915
摘要： The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a first layer of conductively doped semiconductive material and only one layer of conductive nitride. The integrated circuitry further comprises a second field effect transistor supported by the substrate. The second field effect transistor comprises a second transistor gate assembly which includes a second layer of conductively doped semiconductor material and at least two layers of conductive nitride. The invention also encompasses a field effect transistor assembly which includes a channel region and an insulative material along the channel region. The transistor assembly further includes a gate stack proximate the channel region. The gate stack includes a first conductive nitride layer separated from the channel region by the insulative material. The stack further includes a conductively doped semiconductive material proximate the first conductive nitride layer, and a second conductive nitride layer separated from the first conductive nitride layer by the conductively doped semiconductive material. Additionally, the invention encompasses methods of forming field effect transistors, and methods of forming integrated circuitry.
摘要翻译：本发明包括集成电路，其包括半导体材料衬底和由衬底支撑的第一场效应晶体管。第一场效应晶体管包括第一晶体管栅极组件，其包括第一导电掺杂半导体材料层和仅一层导电氮化物。集成电路还包括由衬底支撑的第二场效应晶体管。第二场效应晶体管包括第二晶体管栅极组件，其包括导电掺杂半导体材料的第二层和至少两层导电氮化物。本发明还包括场效应晶体管组件，其包括沟道区和沿着沟道区的绝缘材料。晶体管组件还包括靠近沟道区的栅极堆叠。栅极堆叠包括通过绝缘材料与沟道区分离的第一导电氮化物层。堆叠还包括靠近第一导电氮化物层的导电掺杂半导体材料，以及通过导电掺杂的半导体材料与第一导电氮化物层分离的第二导电氮化物层。此外，本发明包括形成场效应晶体管的方法以及形成集成电路的方法。

3. 发明授权

US06498378B1 Methods of forming field effect transistors and integrated circuitry 有权
标题翻译：场效应晶体管和集成电路
公开(公告)号：US06498378B1
公开(公告)日：2002-12-24
申请号：US09708360
申请日：2000-11-07
申请人： Fernando Gonzalez , Chandra Mouli
发明人： Fernando Gonzalez , Chandra Mouli
IPC分类号： H01L2972
CPC分类号： H01L21/28194 , H01L21/28044 , H01L21/28088 , H01L21/28114 , H01L21/28176 , H01L21/28202 , H01L21/28247 , H01L21/82345 , H01L21/823842 , H01L29/42372 , H01L29/4925 , H01L29/4941 , H01L29/4966 , H01L29/517 , H01L29/518 , Y10S257/915
摘要： The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a first layer of conductively doped semiconductive material and only one layer of conductive nitride. The integrated circuitry further comprises a second field effect transistor supported by the substrate. The second field effect transistor comprises a second transistor gate assembly which includes a second layer of conductively doped semiconductor material and at least two layers of conductive nitride. The invention also encompasses a field effect transistor assembly which includes a channel region and an insulative material along the channel region. The transistor assembly further includes a gate stack proximate the channel region. The gate stack includes a first conductive nitride layer separated from the channel region by the insulative material. The stack further includes a conductively doped semiconductive material proximate the first conductive nitride layer, and a second conductive nitride layer separated from the first conductive nitride layer by the conductively doped semiconductive material. Additionally, the invention encompasses methods of forming field effect transistors, and methods of forming integrated circuitry.
摘要翻译：本发明包括集成电路，其包括半导体材料衬底和由衬底支撑的第一场效应晶体管。第一场效应晶体管包括第一晶体管栅极组件，其包括第一导电掺杂半导体材料层和仅一层导电氮化物。集成电路还包括由衬底支撑的第二场效应晶体管。第二场效应晶体管包括第二晶体管栅极组件，其包括导电掺杂半导体材料的第二层和至少两层导电氮化物。本发明还包括场效应晶体管组件，其包括沟道区和沿着沟道区的绝缘材料。晶体管组件还包括靠近沟道区的栅极堆叠。栅极堆叠包括通过绝缘材料与沟道区分离的第一导电氮化物层。堆叠还包括靠近第一导电氮化物层的导电掺杂半导体材料，以及通过导电掺杂的半导体材料与第一导电氮化物层分离的第二导电氮化物层。此外，本发明包括形成场效应晶体管的方法以及形成集成电路的方法。

4. 发明授权

US06486030B2 Methods of forming field effect transistors and integrated circuitry including TiN gate element 有权
标题翻译：形成场效应晶体管和集成电路的方法
公开(公告)号：US06486030B2
公开(公告)日：2002-11-26
申请号：US09810752
申请日：2001-03-15
申请人： Fernando Gonzalez , Chandra Mouli
发明人： Fernando Gonzalez , Chandra Mouli
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/28044 , H01L21/28088 , H01L21/28114 , H01L21/28176 , H01L21/28202 , H01L21/28247 , H01L21/82345 , H01L21/823842 , H01L29/42372 , H01L29/4925 , H01L29/4941 , H01L29/4966 , H01L29/517 , H01L29/518 , Y10S257/915
摘要： The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a first layer of conductively doped semiconductive material and only one layer of conductive nitride. The integrated circuitry further comprises a second field effect transistor supported by the substrate. The second field effect transistor comprises a second transistor gate assembly which includes a second layer of conductively doped semiconductor material and at least two layers of conductive nitride. The invention also encompasses a field effect transistor assembly which includes a channel region and an insulative material along the channel region. The transistor assembly further includes a gate stack proximate the channel region. The gate stack includes a first conductive nitride layer separated from the channel region by the insulative material. The stack further includes a conductively doped semiconductive material proximate the first conductive nitride layer, and a second conductive nitride layer separated from the first conductive nitride layer by the conductively doped semiconductive material. Additionally, the invention encompasses methods of forming field effect transistors, and methods of forming integrated circuitry.
摘要翻译：本发明包括集成电路，其包括半导体材料衬底和由衬底支撑的第一场效应晶体管。第一场效应晶体管包括第一晶体管栅极组件，其包括第一导电掺杂半导体材料层和仅一层导电氮化物。集成电路还包括由衬底支撑的第二场效应晶体管。第二场效应晶体管包括第二晶体管栅极组件，其包括导电掺杂半导体材料的第二层和至少两层导电氮化物。本发明还包括场效应晶体管组件，其包括沟道区和沿着沟道区的绝缘材料。晶体管组件还包括靠近沟道区的栅极堆叠。栅极堆叠包括通过绝缘材料与沟道区分离的第一导电氮化物层。堆叠还包括靠近第一导电氮化物层的导电掺杂半导体材料，以及通过导电掺杂的半导体材料与第一导电氮化物层分离的第二导电氮化物层。此外，本发明包括形成场效应晶体管的方法以及形成集成电路的方法。

5. 发明授权

US08501602B2 Method of manufacturing devices having vertical junction edge 有权
标题翻译：制造具有垂直接合边缘的器件的方法
公开(公告)号：US08501602B2
公开(公告)日：2013-08-06
申请号：US13336516
申请日：2011-12-23
申请人： Fernando Gonzalez , Chandra Mouli
发明人： Fernando Gonzalez , Chandra Mouli
IPC分类号： H01L21/425
CPC分类号： H01L29/66636 , H01L21/2257 , H01L21/823481 , H01L21/823864 , H01L21/823878 , H01L29/41783 , H01L29/7834
摘要： Techniques for forming devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an oxide. Cavities may be formed in the oxide and filled with a conductive material, such a doped polysilicon. Vertical junctions are formed between the polysilicon and the exposed substrate at the trench edges such that during a thermal cycle, the doped polysilicon will out-diffuse doping elements into the adjacent single crystal silicon advantageously forming a diode extension having desirable properties.
摘要翻译：用于形成诸如晶体管的器件的技术具有垂直的接合边缘。更具体地说，在沟槽中形成浅沟槽并填充氧化物。可以在氧化物中形成空穴并填充导电材料，例如掺杂的多晶硅。在沟槽边缘处在多晶硅和暴露的衬底之间形成垂直结，使得在热循环期间，掺杂多晶硅将掺杂元素扩散到相邻的单晶硅中，有利地形成具有期望性质的二极管延伸。

6. 发明授权

US07332790B2 Semiconductor device having an active area partially isolated by a lateral cavity 有权
标题翻译：半导体器件具有通过侧向腔部分隔离的有源区
公开(公告)号：US07332790B2
公开(公告)日：2008-02-19
申请号：US11458967
申请日：2006-07-20
申请人： Fernando Gonzalez , Chandra Mouli , Lyle Jones
发明人： Fernando Gonzalez , Chandra Mouli , Lyle Jones
IPC分类号： H01L27/105 , H01L29/78 , H01L21/546
CPC分类号： H01L27/10873 , H01L21/26506 , H01L21/76235 , H01L21/76264 , H01L21/76281 , H01L21/76289 , H01L21/764 , H01L21/823412 , H01L21/823481 , H01L21/84 , H01L27/0214 , H01L27/10811 , H01L27/10844 , H01L27/11521 , H01L27/1203 , H01L28/91 , H01L29/7846
摘要： A process of making a partial silicon-on-insulator ledge is disclosed. A deep implantation region is created in a substrate. During a lateral cavity etch, the deep implantation region resists etching. The lateral cavity etch acts to partially isolate an active area above the deep implantation region. The deep implantation region is formed at various process stages according to embodiments. An active device is also disclosed that is achieved by the process. A system is also disclosed that uses the active device.
摘要翻译：公开了一种制造绝缘体上部分硅片的工艺。在衬底中产生深的注入区域。在横向腔蚀刻期间，深注入区域抵抗蚀刻。侧腔蚀刻用于部分隔离深注入区域上方的有效区域。根据实施例，在各种处理阶段形成深注入区域。还公开了通过该过程实现的主动装置。还公开了一种使用有源器件的系统。

7. 发明申请

US20060220169A1 Device having conductive material disposed in a cavity formed in an isolation oxide disposed in a trench 有权
标题翻译：具有设置在形成在设置在沟槽中的隔离氧化物中的空腔中的导电材料的器件
公开(公告)号：US20060220169A1
公开(公告)日：2006-10-05
申请号：US11438771
申请日：2006-05-23
申请人： Fernando Gonzalez , Chandra Mouli
发明人： Fernando Gonzalez , Chandra Mouli
IPC分类号： H01L29/00
CPC分类号： H01L29/66636 , H01L21/2257 , H01L21/823481 , H01L21/823864 , H01L21/823878 , H01L29/41783 , H01L29/7834
摘要： Devices, such as transistors, having vertical junction edges. More specifically, shallow trenches are formed in a substrate and filled with an isolation oxide. Cavities are formed in the isolation oxide and filled with a conductive material, such a doped polysilicon. Doped regions may be formed in the substrate directly adjacent the conductive material to form vertical junctions between the polysilicon and the exposed substrate at the trench sidewalls.
摘要翻译：诸如晶体管的器件具有垂直的接合边缘。更具体地说，浅沟槽形成在衬底中并填充有隔离氧化物。在隔离氧化物中形成空穴，并填充有导电材料，例如掺杂的多晶硅。掺杂区域可以形成在直接邻近导电材料的衬底中，以在沟槽侧壁处形成多晶硅和暴露衬底之间的垂直结。

8. 发明授权

US06597045B2 Semiconductor raised source-drain structure 有权
标题翻译：半导体升高源极 - 漏极结构
公开(公告)号：US06597045B2
公开(公告)日：2003-07-22
申请号：US10008655
申请日：2001-11-09
申请人： Fernando Gonzalez , Chandra Mouli
发明人： Fernando Gonzalez , Chandra Mouli
IPC分类号： H01L2710
CPC分类号： H01L29/4991 , H01L21/28512 , H01L21/7682 , H01L21/76895 , H01L23/5226 , H01L29/41775 , H01L29/41783 , H01L29/4983 , H01L29/66492 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure which includes a raised source, a raised drain, a gate located between the source and the drain, a first capping layer in communication with at least a portion of the gate and the source, a second capping layer in communication with at least a portion of the gate and the drain, a first portion of a gate oxide region in communication with at least a portion of the gate and the source, a second portion of a gate oxide region in communication with at least a portion of the gate and the drain. The source, the gate, the first capping layer, and the first portion of a gate oxide region define a first gap. The drain, the gate, the second capping layer, and the second portion of a gate oxide region define a second gap. The structure also includes a first junction area located beneath the first gap, the gate and the source and a second junction area located beneath the second gap, the gate and the drain.
摘要翻译：一种半导体结构，其包括升高源极，升高的漏极，位于源极和漏极之间的栅极，与栅极和源极的至少一部分连通的第一覆盖层，至少与第一覆盖层连通的第二覆盖层栅极和漏极的一部分，与栅极和源极的至少一部分连通的栅极氧化物区域的第一部分，栅极氧化物区域的与栅极的至少一部分连通的第二部分，以及排水。源极，栅极，第一覆盖层和栅极氧化物区域的第一部分限定第一间隙。漏极，栅极，第二覆盖层和栅极氧化物区域的第二部分限定第二间隙。该结构还包括位于第一间隙下方的第一接合区域，栅极和源极以及位于第二间隙下方的栅极和漏极的第二接合区域。

9. 发明授权

US06271067B1 Methods of forming field effect transistors and field effect transistor circuitry 失效
公开(公告)号：US06271067B1
公开(公告)日：2001-08-07
申请号：US09032267
申请日：1998-02-27
申请人： Fernando Gonzalez , Chandra Mouli
发明人： Fernando Gonzalez , Chandra Mouli
IPC分类号： H01L218238
CPC分类号： H01L27/0727
摘要： Methods of forming field effect transistors and resultant field effect transistor circuitry are described. In one embodiment, a semiconductive substrate includes a field effect transistor having a body. A first resistive element is received by the substrate and connected between the transistor's gate and the body. A second resistive element is received by the substrate and connected between the body and a reference voltage node. The first and second resistive elements form a voltage divider which is configured to selectively change threshold voltages of the field effect transistor with state changes in the gate voltage. In a preferred embodiment, first and second diode assemblies are positioned over the substrate and connected between the gate and body, and the body and a reference voltage node to provide the voltage divider.

10. 发明授权

US06221708B1 Field effect transistor assemblies, integrated circuitry, and methods of forming field effect transistors and integrated circuitry 有权
公开(公告)号：US06221708B1
公开(公告)日：2001-04-24
申请号：US09360230
申请日：1999-07-23
申请人： Fernando Gonzalez , Chandra Mouli
发明人： Fernando Gonzalez , Chandra Mouli
IPC分类号： H01L2972
CPC分类号： H01L21/28194 , H01L21/28044 , H01L21/28088 , H01L21/28114 , H01L21/28176 , H01L21/28202 , H01L21/28247 , H01L21/82345 , H01L21/823842 , H01L29/42372 , H01L29/4925 , H01L29/4941 , H01L29/4966 , H01L29/517 , H01L29/518 , Y10S257/915
摘要： The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a first layer of conductively doped semiconductive material and only one layer of conductive nitride. The integrated circuitry further comprises a second field effect transistor supported by the substrate. The second field effect transistor comprises a second transistor gate assembly which includes a second layer of conductively doped semiconductor material and at least two layers of conductive nitride. The invention also encompasses a field effect transistor assembly which includes a channel region and an insulative material along the channel region. The transistor assembly further includes a gate stack proximate the channel region. The gate stack includes a first conductive nitride layer separated from the channel region by the insulative material. The stack further includes a conductively doped semiconductive material proximate the first conductive nitride layer, and a second conductive nitride layer separated from the first conductive nitride layer by the conductively doped semiconductive material. Additionally, the invention encompasses methods of forming field effect transistors, and methods of forming integrated circuitry.

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