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1. 发明授权

US09029172B2 On-chip poly-to-contact process monitoring and reliability evaluation system and method of use 有权
标题翻译：片上多点接触过程监控与可靠性评估系统及使用方法
公开(公告)号：US09029172B2
公开(公告)日：2015-05-12
申请号：US13354547
申请日：2012-01-20
申请人： Fen Chen , Roger A. Dufresne , Timothy D. Sullivan , Yanfeng Wang
发明人： Fen Chen , Roger A. Dufresne , Timothy D. Sullivan , Yanfeng Wang
IPC分类号： H01L21/00 , H01L21/66
CPC分类号： H01L22/34 , H01L22/12 , H01L2924/00 , H01L2924/0002
摘要： An on-chip poly-to-contact process monitoring and reliability evaluation system and method of use are provided. A method includes determining a breakdown electrical field of each of one or more shallow trench isolation (STI) measurement structures corresponding to respective one or more original semiconductor structures. The method further includes determining a breakdown voltage of each of one or more substrate measurement structures corresponding to the respective one or more original semiconductor structures. The method further includes determining a space between a gate and a contact of each of the one or more original semiconductor structures based on the determined breakdown electrical field and the determined breakdown voltage.
摘要翻译：提供片上多点接触式过程监测和可靠性评估系统及其使用方法。一种方法包括确定与相应的一个或多个原始半导体结构相对应的一个或多个浅沟槽隔离（STI）测量结构中的每一个的击穿电场。该方法还包括确定与相应的一个或多个原始半导体结构相对应的一个或多个衬底测量结构中的每一个的击穿电压。该方法还包括基于所确定的击穿电场和所确定的击穿电压，确定一个或多个原始半导体结构中的每一个的栅极和触点之间的空间。

2. 发明授权

US08917104B2 Analyzing EM performance during IC manufacturing 有权
标题翻译：分析IC制造过程中的EM性能
公开(公告)号：US08917104B2
公开(公告)日：2014-12-23
申请号：US13222306
申请日：2011-08-31
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/3187 , G01R31/28
CPC分类号： G01R31/2858
摘要： A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.
摘要翻译：用于监测电迁移（EM）性能的测试结构，系统和方法。描述了包括测试结构阵列的系统，其中每个测试结构包括：具有四点电阻测量的EM电阻器，其中第一和第二端子提供电流输入，第三和第四端子提供电压测量; 耦合到所述EM电阻器的第一端子以提供测试电流的第一晶体管; 由一对开关晶体管获得的电压测量，其栅极由选择开关控制，并且其漏极用于在第三和第四端子处提供电压测量。还包括用于选择性地激活测试结构阵列之一的选择开关的解码器; 以及用于输出所选择的测试结构的电压测量的一对输出。

3. 发明授权

US08754655B2 Test structure, method and circuit for simultaneously testing time dependent dielectric breakdown and electromigration or stress migration 失效
标题翻译：测试结构，方法和电路，用于同时测试时间依赖介电击穿和电迁移或应力迁移
公开(公告)号：US08754655B2
公开(公告)日：2014-06-17
申请号：US13207485
申请日：2011-08-11
申请人： David G. Brochu, Jr. , Fen Chen , Roger A. Dufresne , Travis S. Merrill , Michael A. Shinosky
发明人： David G. Brochu, Jr. , Fen Chen , Roger A. Dufresne , Travis S. Merrill , Michael A. Shinosky
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.
摘要翻译：用于同时测试电迁移或应力迁移的测试结构在集成电路中的时间依赖介质击穿失效，使用布置为桥接平衡电路的四个测试结构的测试电路和使用测试电路的测试方法。测试结构的电迁移或应力迁移部分包括通过导电通孔串联连接的导线段的通孔链，形成在集成电路的至少两个相邻布线层中的线段。测试结构的时间依赖介质击穿部分包括在与数字化的线结构相同的布线级别中与所述线段的少于整个部分相邻的所述至少两个相邻布线层之一中的数字化线结构。

4. 发明申请

US20130049793A1 ANALYZING EM PERFORMANCE DURING IC MANUFACTURING 有权
标题翻译：在IC制造过程中分析EM性能
公开(公告)号：US20130049793A1
公开(公告)日：2013-02-28
申请号：US13222306
申请日：2011-08-31
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/26 , G01R31/02
CPC分类号： G01R31/2858
摘要： A testing structure, system and method for monitoring electro-migration (EM) performance. A system is described that includes an array of testing structures, wherein each testing structure includes: an EM resistor having four point resistive measurement, wherein a first and second terminals provide current input and a third and fourth terminals provide a voltage measurement; a first transistor coupled to a first terminal of the EM resistor for supplying a test current; the voltage measurement obtained from a pair of switching transistors whose gates are controlled by a selection switch and whose drains are utilized to provide a voltage measurement across the third and fourth terminals. Also included is a decoder for selectively activating the selection switch for one of the array of testing structures; and a pair of outputs for outputting the voltage measurement of a selected testing structure.
摘要翻译：用于监测电迁移（EM）性能的测试结构，系统和方法。描述了包括测试结构阵列的系统，其中每个测试结构包括：具有四点电阻测量的EM电阻器，其中第一和第二端子提供电流输入，第三和第四端子提供电压测量; 耦合到所述EM电阻器的第一端子以提供测试电流的第一晶体管; 由一对开关晶体管获得的电压测量，其栅极由选择开关控制，并且其漏极用于在第三和第四端子处提供电压测量。还包括用于选择性地激活测试结构阵列之一的选择开关的解码器; 以及用于输出所选择的测试结构的电压测量的一对输出。

5. 发明申请

US20130038334A1 TEST STRUCTURE, METHOD AND CIRCUIT FOR SIMULTANEOUSLY TESTING TIME DEPENDENT DIELECTRIC BREAKDOWN AND ELECTROMIGRATION OR STRESS MIGRATION 失效
标题翻译：测试结构，方法和电路同时测试时间依赖电介质断开和电力或应力移动
公开(公告)号：US20130038334A1
公开(公告)日：2013-02-14
申请号：US13207485
申请日：2011-08-11
申请人： David G. Brochu, JR. , Fen Chen , Roger A. Dufresne , Travis S. Merrill , Michael A. Shinosky
发明人： David G. Brochu, JR. , Fen Chen , Roger A. Dufresne , Travis S. Merrill , Michael A. Shinosky
IPC分类号： G01R31/02
CPC分类号： G01R31/2858
摘要： Test structures for simultaneously testing for electromigration or stress migration fails and time dependent dielectric breakdown fails in integrated circuits, test circuits using four test structures arranged as a bridge balance circuit and methods of testing using the test circuits. The electromigration or stress migration portions of the test structures include via chains of wire segments connected in series by electrically conductive vias, the wire segments formed in at least two adjacent wiring levels of an integrated circuit. The time dependent dielectric breakdown portions of the test structures include digitized wire structures in one of the at least two adjacent wiring levels adjacent to a less than whole portion of the wire segments in the same wiring level as the digitized wire structures.
摘要翻译：用于同时测试电迁移或应力迁移的测试结构在集成电路中的时间依赖介质击穿失效，使用布置为桥接平衡电路的四个测试结构的测试电路和使用测试电路的测试方法。测试结构的电迁移或应力迁移部分包括通过导电通孔串联连接的导线段的通孔链，形成在集成电路的至少两个相邻布线层中的线段。测试结构的时间依赖介质击穿部分包括在与数字化的线结构相同的布线级别中与所述线段的少于整个部分相邻的所述至少两个相邻布线层之一中的数字化线结构。

6. 发明申请

US20130106452A1 REAL-TIME ON-CHIP EM PERFORMANCE MONITORING 有权
标题翻译：实时片上EM性能监控
公开(公告)号：US20130106452A1
公开(公告)日：2013-05-02
申请号：US13282090
申请日：2011-10-26
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/3187
CPC分类号： G01R31/3004
摘要： An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.
摘要翻译：用于监测电迁移（EM）性能的集成电路，测试结构和方法。描述了一种包括用于测量片上电迁移（EM）性能的方法的方法，包括：提供用应力电流连续供电的第一片上传感器; 提供仅在具有额定电流的测量周期期间供电的第二片上传感器; 在一系列测量周期中的每一个期间，从第一片上传感器获得第一电阻测量值和来自第二片上传感器的第二电阻测量值; 并处理第一和第二电阻测量。

7. 发明授权

US08890556B2 Real-time on-chip EM performance monitoring 有权
标题翻译：实时片上EM性能监控
公开(公告)号：US08890556B2
公开(公告)日：2014-11-18
申请号：US13282090
申请日：2011-10-26
申请人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
发明人： Fen Chen , Roger A. Dufresne , Kai D. Feng , Richard J. St-Pierre
IPC分类号： G01R31/3187 , G01R31/30
CPC分类号： G01R31/3004
摘要： An integrated circuit, testing structure, and method for monitoring electro-migration (EM) performance. A method is described that includes method for measuring on-chip electro-migration (EM) performance, including: providing a first on-chip sensor continuously powered with a stress current; providing a second on-chip sensor that is powered only during measurement cycles with a nominal current; obtaining a first resistance measurement from the first on-chip sensor and a second resistance measurement from the second on-chip sensor during each of a series of measurement cycles; and processing the first and second resistance measurements.
摘要翻译：用于监测电迁移（EM）性能的集成电路，测试结构和方法。描述了一种包括用于测量片上电迁移（EM）性能的方法的方法，包括：提供用应力电流连续供电的第一片上传感器; 提供仅在具有额定电流的测量周期期间供电的第二片上传感器; 在一系列测量周期中的每一个期间，从第一片上传感器获得第一电阻测量值和来自第二片上传感器的第二电阻测量值; 并处理第一和第二电阻测量。

8. 发明申请

US20120299188A1 WIRING STRUCTURE AND METHOD OF FORMING THE STRUCTURE 有权
标题翻译：导线结构及形成结构的方法
公开(公告)号：US20120299188A1
公开(公告)日：2012-11-29
申请号：US13114079
申请日：2011-05-24
申请人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Anthony K. Stamper , Timothy D. Sullivan
IPC分类号： H01L23/485 , H01L21/768
CPC分类号： H01L21/76816 , H01L21/76843 , H01L23/5283 , H01L23/53223 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a wiring structure and method of forming the structure with a conductive diffusion barrier layer having a thick upper portion and thin lower portion. The thicker upper portion is located at the junction between the wiring structure and the adjacent dielectric materials. The thicker upper portion: (1) minimizes metal ion diffusion and, thereby TDDB; (2) allows a wire width to dielectric space width ratio that is optimal for low TDDB to be achieved at the top of the wiring structure; and (3) provides a greater surface area for via landing. The thinner lower portion: (1) allows a different wire width to dielectric space width ratio to be maintained in the rest of the wiring structure in order to balance other competing factors; (2) allows a larger cross-section of wire to reduce current density and, thereby reduce EM; and (3) avoids an increase in wiring structure resistivity.
摘要翻译：公开了一种具有导电扩散阻挡层的结构的布线结构和方法，所述导电扩散阻挡层具有较厚的上部和较薄的下部。较厚的上部位于布线结构和相邻电介质材料之间的接合处。较厚的上部：（1）最小化金属离子扩散，从而使TDDB; （2）允许在布线结构的顶部实现对于低TDDB最佳的电线宽度与电介质空间宽度比; 和（3）为通孔着陆提供更大的表面积。较薄的下部：（1）允许在布线结构的其余部分中保持不同的导线宽度与电介质空间宽度比，以平衡其他竞争因素; （2）允许更大的导线截面减小电流密度，从而减少EM; 和（3）避免了布线结构电阻率的增加。

9. 发明授权

US08018017B2 Thermo-mechanical cleavable structure 有权
标题翻译：热机械可切割结构
公开(公告)号：US08018017B2
公开(公告)日：2011-09-13
申请号：US10905905
申请日：2005-01-26
申请人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
发明人： Fen Chen , Cathryn J. Christiansen , Richard S. Kontra , Tom C. Lee , Alvin W. Strong , Timothy D. Sullivan , Joseph E. Therrien
IPC分类号： H01L31/058
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A thermo-mechanical cleavable structure is provided and may be used as a programmable fuse for integrated circuits. As applied to a programmable fuse, the thermo-mechanical cleavable structure includes an electrically conductive cleavable layer adjacent to a thermo-mechanical stressor. As electricity is passed through the cleavable layer, the cleavable layer and the thermo-mechanical stressor are heated and gas evolves from the thermo-mechanical stressor. The gas locally insulates the thermo-mechanical stressor, causing local melting adjacent to the bubbles in the thermo-mechanical stressor and the cleavable structure forming cleaving sites. The melting also interrupts the current flow through the cleavable structure so the cleavable structure cools and contracts. The thermo-mechanical stressor also contracts due to a phase change caused by the evolution of gas therefrom. As the thermo-mechanical cleavable structure cools, the cleaving sites expand causing gaps to be permanently formed therein.
摘要翻译：提供了一种热机械可切割结构，可用作集成电路的可编程保险丝。如应用于可编程保险丝，热机械可切割结构包括与热机械应力源相邻的导电可切割层。当电通过可切割层时，可切割层和热机械应力器被加热并且气体从热机械应力源逸出。气体将热机械应力局部绝缘，导致邻近热机械应力的气泡局部熔化，形成裂开位置的可切割结构。熔化还中断当前通过可切割结构的流动，因此可切割结构冷却和收缩。热机械应力还由于由其产生的气体引起的相变而收缩。当热机械可裂解结构冷却时，裂解位置膨胀，导致间隙永久形成。

10. 发明授权

US07231617B2 Determination of grain sizes of electrically conductive lines in semiconductor integrated circuits 有权
标题翻译：确定半导体集成电路中导电线的晶粒尺寸
公开(公告)号：US07231617B2
公开(公告)日：2007-06-12
申请号：US10711418
申请日：2004-09-17
申请人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
发明人： Fen Chen , Jeffrey P. Gambino , Jason P. Gill , Baozhen Li , Timothy D. Sullivan
IPC分类号： G06F17/50
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： Novel structures and methods for evaluating lines in semiconductor integrated circuits. A first plurality of lines can be formed on a wafer each of which comprises multiple line sections. All the line sections are of the same length. The electrical resistances of the line sections are measured. Then, a first line geometry adjustment is determined based on the electrical resistances of all the sections of all the lines. The first line geometry adjustment represents an effective reduction of cross-section size of the lines due to grain boundary electrical resistance. A second plurality of lines of same length and thickness can be formed on the same wafer. Then, second and third line geometry adjustments can be determined based on the electrical resistances of these lines measured at different temperatures. The second and third line geometry adjustments represent an effective reduction of cross-section size of the lines due to grain boundary electrical resistance and line surface roughness.
摘要翻译：用于评估半导体集成电路中的线路的新型结构和方法。可以在每个包括多个线段的晶片上形成第一组多条线。所有线段长度相同。测量线路段的电阻。然后，基于所有线的所有部分的电阻来确定第一线几何形状调整。第一行几何调整表示由于晶界电阻而导致的线的横截面尺寸的有效减小。相同长度和厚度的第二组多条线可以形成在同一晶片上。然后，可以基于在不同温度下测量的这些线的电阻来确定第二和第三线几何调整。第二和第三线几何调整表示由于晶界电阻和线表面粗糙度导致的线的横截面尺寸的有效减小。

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