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1. 发明授权

US09231519B2 Temperature compensation for oscillator 有权
标题翻译：振荡器温度补偿
公开(公告)号：US09231519B2
公开(公告)日：2016-01-05
申请号：US13976942
申请日：2012-03-13
申请人： Fangxing Wei , Yongping Fan
发明人： Fangxing Wei , Yongping Fan
IPC分类号： H03L1/00 , H03B5/04 , H03B5/12
CPC分类号： H03B5/04 , H03B5/1215 , H03B5/1228 , H03B5/1243 , H03B5/1265
摘要： A temperature compensation apparatus may include a sense circuit configured to produce a sense voltage that is dependent on temperature and a temperature compensation circuit configured to receive the sense voltage and produce a temperature compensation control signal to control a compensation capacitor array of an oscillator. The temperature compensation circuit may be configured to calibrate the control signal to have a first value at a first temperature. The temperature compensation circuit may also be configured to calibrate a trimming level (e.g., slope) of the control signal.
摘要翻译：温度补偿装置可以包括被配置为产生取决于温度的感测电压的感测电路和被配置为接收感测电压并产生温度补偿控制信号以控制振荡器的补偿电容器阵列的温度补偿电路。温度补偿电路可以被配置为校准控制信号以具有处于第一温度的第一值。温度补偿电路还可以被配置为校准控制信号的微调电平（例如，斜率）。

2. 发明授权

US06137735A Column redundancy circuit with reduced signal path delay 有权
标题翻译：列冗余电路具有减少的信号路径延迟
公开(公告)号：US06137735A
公开(公告)日：2000-10-24
申请号：US182495
申请日：1998-10-30
申请人： Fangxing Wei , Hirohito Kikukawa , Cynthia Mar
发明人： Fangxing Wei , Hirohito Kikukawa , Cynthia Mar
IPC分类号： G11C11/401 , G06F11/20 , G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/78 , G11C29/808
摘要： The invention discloses a synchronous DRAM having memory elements arranged in rows and columns, the memory elements being accessible by decoding a memory address applied thereto, normal column drivers for activating appropriate memory elements in response to decoded column addresses signals; redundant column drivers distributed throughout memory banks and flexibly selectable to replace faulty columns within multiple blocks within a bank; and switch means for selectively activating the redundant column and preventing the activation of a defective normal column, whereby the column redundancy method and apparatus minimizes the timing difference between a normal and redundant column paths and which minimizes the number of fuses required to be blown in repairing faulty columns addresses.
摘要翻译：本发明公开了一种具有排列成行和列的存储器元件的同步DRAM，存储器元件可通过解码施加到其上的存储器地址来访问，正常列驱动器用于响应于解码的列地址信号激活适当的存储器元件; 分布在整个存储体中的冗余列驱动器，并且可灵活选择以替换存储体内多个块内的故障列; 以及用于选择性地激活冗余列并防止故障正常列的激活的开关装置，由此列冗余方法和装置使正常和冗余列路径之间的定时差最小化，并且使修理中需要熔断的数量最小化错误的列地址。

3. 发明授权

US09112671B2 Gated ring oscillator-based digital eye width monitor for high-speed I/O eye width measurement 有权
标题翻译：基于门控振荡器的数字眼睛宽度监视器，用于高速I / O眼睛宽度测量
公开(公告)号：US09112671B2
公开(公告)日：2015-08-18
申请号：US13976485
申请日：2012-02-07
申请人： Fangxing Wei , Subratakumar Mandal
发明人： Fangxing Wei , Subratakumar Mandal
IPC分类号： H03K3/03 , H04L7/00 , H03K5/13 , H03K5/00
CPC分类号： H04L7/0087 , H03K3/0315 , H03K5/133 , H03K2005/00052
摘要： A novel digital eye width monitor (DEWM) system and method are disclosed. The DEWM system provides on-die capability to directly measure the left and right eye-width in picoseconds. The DEWM system measures the time from the phase interpolator (PI) clock position (data eye center, left edge, right edge) to a reference clock, and calculates the left and right eye width within a single-digit pico-second level of accuracy.
摘要翻译：公开了一种新颖的数字眼宽监视器（DEWM）系统和方法。 DEWM系统提供了直接测量左右眼宽的皮秒能力。 DEWM系统测量从相位插值器（PI）时钟位置（数据眼中心，左边缘，右边缘）到参考时钟的时间，并计算单位数微微秒精度水平的左右眼宽度。

4. 发明申请

US20080224754A1 HIGH-SPEED SERIAL LINK RECEIVER WITH CENTRALLY CONTROLLED OFFSET CANCELLATION AND METHOD 有权
标题翻译：具有中央控制偏移消除和方法的高速串行接收器
公开(公告)号：US20080224754A1
公开(公告)日：2008-09-18
申请号：US12128377
申请日：2008-05-28
申请人： Fangxing Wei , Arif Mahmud
发明人： Fangxing Wei , Arif Mahmud
IPC分类号： H03L5/00
CPC分类号： H04L25/085 , H04L25/06
摘要： A high-speed serial link receiver includes variable offset comparators with centrally controlled offset cancellation. The receiver includes a comparator stage to receive a high-speed differential input signal. Comparator elements of the comparator stage have first and second current sources to provide current to corresponding differential amplifier half-circuits. An offset cancellation controller provides an offset cancellation signal for setting current provided by one of the current sources to at least partially offset an output offset between the differential amplifier half-circuits. A receiver system may be comprised of a plurality of receiver units for receiving a corresponding plurality of channels over high-speed serial links. A state machine may sequentially determine an offset cancellation code for the comparator elements of the receiver units.
摘要翻译：高速串行链路接收器包括具有中央控制偏移消除的可变偏移比较器。接收器包括用于接收高速差分输入信号的比较器级。比较器级的比较器元件具有第一和第二电流源，以向相应的差分放大器半电路提供电流。偏移消除控制器提供偏移消除信号，用于设置由一个电流源提供的电流，以至少部分地偏移差分放大器半电路之间的输出偏移。接收机系统可以由用于通过高速串行链路接收对应的多个信道的多个接收机单元组成。状态机可以顺序地确定接收机单元的比较器元件的偏移消除码。

5. 发明申请

US20140204988A1 GATED RING OSCILLATOR-BASED DIGITAL EYE WIDTH MONITOR FOR HIGH-SPEED I/O EYE WIDTH MEASUREMENT 有权
标题翻译：门振荡器基于数字眼睛的宽度监视器，用于高速I / O眼睛宽度测量
公开(公告)号：US20140204988A1
公开(公告)日：2014-07-24
申请号：US13976485
申请日：2012-02-07
申请人： Fangxing Wei , Subratakumar Mandal
发明人： Fangxing Wei , Subratakumar Mandal
IPC分类号： H04L7/00
CPC分类号： H04L7/0087 , H03K3/0315 , H03K5/133 , H03K2005/00052
摘要： A novel digital eye width monitor (DEWM) system and method are disclosed. The DEWM system provides on-die capability to directly measure the left and right eye-width in picoseconds. The DEWM system measures the time from the phase interpolator (PI) clock position (data eye center, left edge, right edge) to a reference clock, and calculates the left and right eye width within a single-digit pico-second level of accuracy.
摘要翻译：公开了一种新颖的数字眼宽监视器（DEWM）系统和方法。 DEWM系统提供了直接测量左右眼宽的皮秒能力。 DEWM系统测量从相位插值器（PI）时钟位置（数据眼中心，左边缘，右边缘）到参考时钟的时间，并计算单位数微微秒精度水平的左右眼宽度。

6. 发明授权

US06831492B1 Common-bias and differential structure based DLL 有权
标题翻译：基于偏差和差分结构的DLL
公开(公告)号：US06831492B1
公开(公告)日：2004-12-14
申请号：US09655552
申请日：2000-09-06
申请人： Saeed Abbasi , Fangxing Wei
发明人： Saeed Abbasi , Fangxing Wei
IPC分类号： H03L706
CPC分类号： H03L7/0812 , H03L7/0891
摘要： A delay-locked loop for outputting a precisely signal relative to an input reference signal includes a plurality of selectively controlled delay elements and a delay element control circuit, including a phase detector for detecting a phase shift between the input reference signal and the delayed output signal and producing an error signal. Each of the delay elements includes a first input associated with a negative output and a second input associated with a positive output, whereby the positive and negative outputs are selectively coupled to a constant voltage source responsive to a first bias voltage and to a ground. The positive and negative outputs are responsive to a second bias voltage and the first and second voltage inputs. The constant voltage source and the positive output are coupled via a first transistor and the constant voltage source and negative output are coupled via being a second transistor.
摘要翻译：用于输出相对于输入参考信号的精确信号的延迟锁定环包括多个选择性控制的延迟元件和延迟元件控制电路，包括用于检测输入参考信号和延迟输出信号之间的相移的相位检测器并产生误差信号。每个延迟元件包括与负输出相关联的第一输入和与正输出相关联的第二输入，由此，正和负输出被选择性地耦合到响应于第一偏置电压和地的恒定电压源。正和负输出响应于第二偏置电压和第一和第二电压输入。恒定电压源和正输出通过第一晶体管耦合，恒压源和负输出通过第二晶体管耦合。

7. 发明授权

US06614675B1 Pipelined content addressable memory with read only element encoding scheme 有权
标题翻译：流水线内容可寻址内存，只读元素编码方案
公开(公告)号：US06614675B1
公开(公告)日：2003-09-02
申请号：US09685699
申请日：2000-10-10
申请人： Carol A. Price , Fangxing Wei
发明人： Carol A. Price , Fangxing Wei
IPC分类号： G11C1500
CPC分类号： G11C15/00
摘要： A content addressable memory (CAM) has a CAM array and a CAM encoder. The CAM array in response to data stored in a memory address of the CAM array matching comparison data, produces a match signal corresponding to the memory address. The CAM encoder receives the match signal and using encoded cells, produces the memory address corresponding to the match signal.
摘要翻译：内容可寻址存储器（CAM）具有CAM阵列和CAM编码器。 CAM阵列响应存储在CAM阵列的存储器地址中的数据匹配比较数据，产生对应于存储器地址的匹配信号。 CAM编码器接收匹配信号并使用编码单元，产生对应于匹配信号的存储器地址。

8. 发明申请

US20140093014A1 SYSTEM TIMING MARGIN IMPROVEMENT OF HIGH SPEED I/O INTERCONNECT LINKS BY USING FINE TRAINING OF PHASE INTERPOLATOR 有权
标题翻译：通过使用相位插补器的精细训练来实现高速I / O互连链路的系统时序改进
公开(公告)号：US20140093014A1
公开(公告)日：2014-04-03
申请号：US13631874
申请日：2012-09-29
申请人： Fangxing Wei , Subratakumar Mandal
发明人： Fangxing Wei , Subratakumar Mandal
IPC分类号： H04B1/16
CPC分类号： H04L7/0087 , H04B1/16 , H04L1/205 , H04L7/0016 , H04L7/0025 , H04L7/10
摘要： Methods and apparatus for improving system timing margin of high speed I/O (input/output) interconnect links by using fine training of a phase interpolator are described. In some embodiments, I/O links use forward clock architecture to send data from transmit driver to receiver logic. Moreover, at the receiver side, Phase Interpolator (PI) logic may be used to place the sampling clock at the center of the valid data window or eye. In an embodiment, a Digital Eye Width Monitor (DEWM) logic may be used to measure data eye width in real time. Other embodiments are also disclosed.
摘要翻译：描述了通过使用相位内插器的精细训练来提高高速I / O（输入/输出）互连链路的系统定时裕度的方法和装置。在一些实施例中，I / O链路使用正向时钟架构将数据从发射驱动器发送到接收机逻辑。此外，在接收机侧，可以使用相位插值器（PI）逻辑将采样时钟放置在有效数据窗口或眼睛的中心。在一个实施例中，可以使用数字眼睛宽度监视器（DEWM）逻辑来实时测量数据眼睛宽度。还公开了其他实施例。

9. 发明授权

US08059756B2 High-speed serial link receiver with centrally controlled offset cancellation and method 有权
标题翻译：具有中央控制偏移消除和方法的高速串行接收器
公开(公告)号：US08059756B2
公开(公告)日：2011-11-15
申请号：US12128377
申请日：2008-05-28
申请人： Fangxing Wei , Arif Mahmud
发明人： Fangxing Wei , Arif Mahmud
IPC分类号： H04L27/00
CPC分类号： H04L25/085 , H04L25/06
摘要： A high-speed serial link receiver includes variable offset comparators with centrally controlled offset cancellation. The receiver includes a comparator stage to receive a high-speed differential input signal. Comparator elements of the comparator stage have first and second current sources to provide current to corresponding differential amplifier half-circuits. An offset cancellation controller provides an offset cancellation signal for setting current provided by one of the current sources to at least partially offset an output offset between the differential amplifier half-circuits. A receiver system may be comprised of a plurality of receiver units for receiving a corresponding plurality of channels over high-speed serial links. A state machine may sequentially determine an offset cancellation code for the comparator elements of the receiver units.
摘要翻译：高速串行链路接收器包括具有中央控制偏移消除的可变偏移比较器。接收器包括用于接收高速差分输入信号的比较器级。比较器级的比较器元件具有第一和第二电流源，以向相应的差分放大器半电路提供电流。偏移消除控制器提供偏移消除信号，用于设置由一个电流源提供的电流，以至少部分地偏移差分放大器半电路之间的输出偏移。接收机系统可以由用于通过高速串行链路接收对应的多个信道的多个接收机单元组成。状态机可以顺序地确定接收机单元的比较器元件的偏移消除码。

10. 发明授权

US07391824B2 High-speed serial link receiver with centrally controlled offset cancellation and method 有权
标题翻译：具有中央控制偏移消除和方法的高速串行接收器
公开(公告)号：US07391824B2
公开(公告)日：2008-06-24
申请号：US10444310
申请日：2003-05-22
申请人： Fangxing Wei , Arif Mahmud
发明人： Fangxing Wei , Arif Mahmud
IPC分类号： H03K9/00
CPC分类号： H04L25/085 , H04L25/06
摘要： A high-speed serial link receiver includes variable offset comparators with centrally controlled offset cancellation. The receiver includes a comparator stage to receive a high-speed differential input signal. Comparator elements of the comparator stage have first and second current sources to provide current to corresponding differential amplifier half-circuits. An offset cancellation controller provides an offset cancellation signal for setting current provided by one of the current sources to at least partially offset an output offset between the differential amplifier half-circuits. A receiver system may be comprised of a plurality of receiver units for receiving a corresponding plurality of channels over high-speed serial links. A state machine may sequentially determine an offset cancellation code for the comparator elements of the receiver units.
摘要翻译：高速串行链路接收器包括具有中央控制偏移消除的可变偏移比较器。接收器包括用于接收高速差分输入信号的比较器级。比较器级的比较器元件具有第一和第二电流源，以向相应的差分放大器半电路提供电流。偏移消除控制器提供偏移消除信号，用于设置由一个电流源提供的电流，以至少部分地偏移差分放大器半电路之间的输出偏移。接收机系统可以由用于通过高速串行链路接收对应的多个信道的多个接收机单元组成。状态机可以顺序地确定接收机单元的比较器元件的偏移消除码。

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