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1. 发明授权

US07107571B2 Visual analysis and verification system using advanced tools 有权
公开(公告)号：US07107571B2
公开(公告)日：2006-09-12
申请号：US09906920
申请日：2001-07-16
申请人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati , Linard Karklin
发明人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati , Linard Karklin
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , G03F1/26 , G03F1/36 , G03F1/84 , G03F7/70441 , G03F7/705 , G06T7/0004 , G06T2207/30148
摘要： A system and method of analyzing defects on a mask used in lithography are provided. A defect area image is provided as a first input, a set of lithography parameters is provided as a second input, and a set of metrology data is provided as a third input. The defect area image comprises an image of a portion of the mask. A simulated image can be generated in response to the first input. The simulated image comprises a simulation of an image that would be printed on a wafer if the wafer were exposed to a radiation source directed at the portion of the mask. The characteristics of the radiation source comprise the set of lithography parameters and the characteristics of the mask comprise the set of metrology data.

2. 发明授权

US06757645B2 Visual inspection and verification system 有权
公开(公告)号：US06757645B2
公开(公告)日：2004-06-29
申请号：US09130996
申请日：1998-08-07
申请人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati , Linard N. Karklin
发明人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati , Linard N. Karklin
IPC分类号： G06F1750
CPC分类号： G06T7/0004 , G03F1/26 , G03F1/36 , G03F1/84 , G03F7/70441 , G03F7/705 , G06F17/5068 , G06T2207/30148
摘要： A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask. The method may also include providing a second simulated image which is a simulation of the wafer print of the portion of the design mask which corresponds to the portion represented by the defect area image. The method also provides for the comparison of the first and second simulated images in order to determine the printability of any identified potential defects on the photolithography mask. A method of determining the process window effect of any identified potential defects is also provided for.

3. 发明授权

US07523027B2 Visual inspection and verification system 有权
标题翻译：目视检查和验证系统
公开(公告)号：US07523027B2
公开(公告)日：2009-04-21
申请号：US10878847
申请日：2004-06-28
申请人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati , Linard N. Karklin
发明人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati , Linard N. Karklin
IPC分类号： G06F17/50
CPC分类号： G06T7/0004 , G03F1/26 , G03F1/36 , G03F1/84 , G03F7/70441 , G03F7/705 , G06F17/5068 , G06T2207/30148
摘要： A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask. The method may also include providing a second simulated image which is a simulation of the wafer print of the portion of the design mask which corresponds to the portion represented by the defect area image. The method also provides for the comparison of the first and second simulated images in order to determine the printability of any identified potential defects on the photolithography mask. A method of determining the process window effect of any identified potential defects is also provided for.
摘要翻译：提供了一种用于检查用于缺陷的光刻掩模的方法和装置。检查方法包括向图像模拟器提供缺陷区域图像，其中缺陷区域图像是光刻掩模的一部分的图像，并且提供一组光刻参数作为图像模拟器的第二输入。缺陷区域图像可以由检查工具提供，该检查工具使用高分辨率显微镜扫描光刻掩模以获得缺陷，并捕获围绕所识别的潜在缺陷的掩模区域的图像。图像模拟器响应于缺陷区域图像和光刻参数集合而生成第一模拟图像。第一模拟图像是如果将晶片暴露于通过该掩模的该部分的照明源而将被印刷在晶片上的图像的模拟。该方法还可以包括提供第二模拟图像，其是对应于由缺陷区域图像表示的部分的设计掩模的部分的晶片印刷的模拟。该方法还提供了第一和第二模拟图像的比较，以便确定光刻掩模上任何识别的潜在缺陷的可印刷性。还提供了确定任何识别的潜在缺陷的过程窗口效应的方法。

4. 发明授权

US07356788B2 Method and apparatus for data hierarchy maintenance in a system for mask description 有权
标题翻译：用于掩模描述的系统中的数据层级维护的方法和装置
公开(公告)号：US07356788B2
公开(公告)日：2008-04-08
申请号：US10173198
申请日：2002-06-18
申请人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati
发明人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated. As the first program data is maintained in a true hierarchical format, layouts which are operated upon in accordance with this method are able to be processed through conventional design rule checkers. Further, this method is capable of being applied to all types of layouts including light and dark field designs and phase shifting layouts.
摘要翻译：一种用于对分级描述的集成电路布局执行操作的方法和装置，从而提供维护布局的原始层级。该方法包括提供分层描述的布局作为第一输入，并提供与作为第二输入执行的操作相对应的特定操作标准集合。然后可以根据特定的操作标准集在布局上执行掩模操作，其可以包括诸如OPC和诸如NOT和OR的逻辑操作的操作。然后响应于布局操作产生包括对应于分层描述的布局的分层配置的校正数据的第一程序数据，使得如果第一程序数据被应用于平坦化布局，则输出包括表示执行操作的结果的数据将生成布局。由于第一程序数据以真正的分层格式维护，所以根据该方法操作的布局能够通过常规的设计规则检查器进行处理。此外，该方法能够应用于所有类型的布局，包括浅色和暗场设计以及相移布局。

5. 发明授权

US06470489B1 Design rule checking system and method 有权
标题翻译：设计规则检查系统和方法
公开(公告)号：US06470489B1
公开(公告)日：2002-10-22
申请号：US09153783
申请日：1998-09-16
申请人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati
发明人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati
IPC分类号： G06F1750
CPC分类号： G06F17/5081 , G03F1/36 , G06F2217/12
摘要： A method for performing design rule checking on OPC corrected or otherwise corrected designs is described. This method comprises accessing a corrected design and generating a simulated image. The simulated image corresponds to a simulation of an image which would be printed on a wafer if the wafer were exposed to an illumination source directed through the corrected design. The characteristics of the illumination source are determined by a set of lithography parameters. In creating the image, additional characteristics can be used to simulate portions of the fabrication process. However, what is important is that a resulting simulated image is created. The simulated image can then be used by the design rule checker. Importantly, the simulated image can be processed to reduce the number of vertices in the simulated image, relative to the number of vertices in the OPC corrected design layout. Also, the simulated image can be compared with an idea layout image, the results of which can then be used to reduce the amount of information that is needed to perform the design rule checking.
摘要翻译：描述了用于对OPC校正或其他校正的设计执行设计规则检查的方法。该方法包括访问经校正的设计并生成模拟图像。模拟图像对应于如果将晶片暴露于通过校正设计的照明源，则将打印在晶片上的图像的模拟。照明源的特性由一组光刻参数确定。在创建图像时，可以使用附加特征来模拟制造过程的部分。然而，重要的是产生了模拟图像。模拟图像然后可以被设计规则检查器使用。重要的是，可以处理模拟图像以相对于OPC校正设计布局中的顶点数来减少模拟图像中的顶点数量。此外，模拟图像可以与想法布局图像进行比较，其结果可以用于减少执行设计规则检查所需的信息量。

6. 发明授权

US06453452B1 Method and apparatus for data hierarchy maintenance in a system for mask description 有权
标题翻译：用于掩模描述的系统中的数据层级维护的方法和装置
公开(公告)号：US06453452B1
公开(公告)日：2002-09-17
申请号：US09154397
申请日：1998-09-16
申请人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati
发明人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati
IPC分类号： G06F1750
CPC分类号： G06F17/5068
摘要： A method and apparatus for performing an operation on hierarchically described integrated circuit layouts such that the original hierarchy of the layout is maintained is provided. The method comprises providing a hierarchically described layout as a first input and providing a particular set of operating criteria corresponding to the operation to be performed as a second input. The mask operation, which may include operations such as OPC and logical operations such as NOT and OR, is then performed on the layout in accordance with the particular set of operating criteria. A first program data comprising hierarchically configured correction data corresponding to the hierarchically described layout is then generated in response to the layout operation such that if the first program data were applied to the flattened layout an output comprising data representative of the result of performing the operation on the layout would be generated. As the first program data is maintained in a true hierarchical format, layouts which are operated upon in accordance with this method are able to be processed through conventional design rule checkers. Further, this method is capable of being applied to all types of layouts including light and dark field designs and phase shifting layouts.
摘要翻译：一种用于对分级描述的集成电路布局执行操作的方法和装置，从而提供维护布局的原始层级。该方法包括提供分层描述的布局作为第一输入，并提供与作为第二输入执行的操作相对应的特定操作标准集合。然后可以根据特定的操作标准集在布局上执行掩模操作，其可以包括诸如OPC和诸如NOT和OR的逻辑操作的操作。然后响应于布局操作产生包括对应于分层描述的布局的分层配置的校正数据的第一程序数据，使得如果第一程序数据被应用于平坦化布局，则输出包括表示执行操作的结果的数据将生成布局。由于第一程序数据以真正的分层格式维护，所以根据该方法操作的布局能够通过常规的设计规则检查器进行处理。此外，该方法能够应用于所有类型的布局，包括浅色和暗场设计以及相移布局。

7. 发明授权

US06370679B1 Data hierarchy layout correction and verification method and apparatus 有权
标题翻译：数据层次布局校正与验证方法及装置
公开(公告)号：US06370679B1
公开(公告)日：2002-04-09
申请号：US09154415
申请日：1998-09-16
申请人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati
发明人： Fang-Cheng Chang , Yao-Ting Wang , Yagyensh C. Pati
IPC分类号： G06F760
CPC分类号： G03F1/36
摘要： A method and apparatus for the correction of integrated circuit layouts for optical proximity effects which maintains the original true hierarchy of the original layout is provided. Also provided is a method and apparatus for the design rule checking of layouts which have been corrected for optical proximity effects. The OPC correction method comprises providing a hierarchically described integrated circuit layout as a first input, and a particular set of OPC correction criteria as a second input. The integrated circuit layout is then analyzed to identify features of the layout which meet the provided OPC correction criteria. After the areas on the mask which need correction have been identified, optical proximity correction data is generated in response to the particular set of correction criteria. Finally, a first program data is generated which stores the generated optical proximity correction data in a hierarchical structure that corresponds to the hierarchical structure of the integrated circuit layout. As the output correction data is maintained in true hierarchical format, layouts which are OPC corrected according to this method are able to be processed through conventional design rule checkers with no altering of the data.
摘要翻译：提供了用于校正维持原始布局的原始真实层级的光学邻近效应的集成电路布局的方法和装置。还提供了用于对光学邻近效应进行了校正的布局的设计规则检查的方法和装置。 OPC校正方法包括提供分级描述的集成电路布局作为第一输入和作为第二输入的特定的OPC校正标准集合。然后分析集成电路布局以识别满足所提供的OPC校正标准的布局的特征。在已经识别出需要校正的掩模上的区域之后，响应于特定的校正标准集而产生光学邻近校正数据。最后，生成将生成的光学邻近校正数据存储在与集成电路布局的层次结构对应的层次结构中的第一程序数据。由于输出校正数据以真实的分层格式保持，所以根据该方法校正OPC的布局能够通过传统的设计规则检查器进行处理，而不改变数据。

8. 发明授权

US06979519B2 Phase shifting circuit manufacture method and apparatus 有权
标题翻译：相移电路制造方法及装置
公开(公告)号：US06979519B2
公开(公告)日：2005-12-27
申请号：US10843974
申请日：2004-05-12
申请人： Yao-Ting Wang , Yagyensh C. Pati
发明人： Yao-Ting Wang , Yagyensh C. Pati
IPC分类号： G03F1/00 , G03F1/26 , G03F1/30 , G03F1/34 , G03F1/36 , G03F7/14 , G03F7/20 , G06F17/50 , G01F9/00
CPC分类号： G03F7/70283 , G03F1/26 , G03F1/30 , G03F1/34 , G03F1/36 , G03F1/70 , G03F7/2022 , G03F7/70433 , G03F7/70441 , G03F7/705 , G06F17/5068
摘要： A method for manufacturing integrated circuits using opaque field, phase shift masking. One embodiment of the invention includes using a two mask process. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.
摘要翻译：一种使用不透光场，相移屏蔽制造集成电路的方法。本发明的一个实施例包括使用两个掩模过程。第一掩模是不透明场相移掩模，第二掩模是单相结构掩模。使用不透明场上的相移重叠区域将相移窗与不透明场对准。相移掩模主要限定需要相移的区域。单相结构掩模主要限定不需要相移的区域。单相结构掩模还防止相移区域的擦除，并且防止产生否则将由相移掩模产生的不期望的伪影区域。

9. 发明授权

US06566023B2 Phase shifting circuit manufacture method and apparatus 有权
标题翻译：相移电路制造方法及装置
公开(公告)号：US06566023B2
公开(公告)日：2003-05-20
申请号：US10154858
申请日：2002-05-24
申请人： Yao-Ting Wang , Yagyensh C. Pati
发明人： Yao-Ting Wang , Yagyensh C. Pati
IPC分类号： G03F900
CPC分类号： G03F7/70283 , G03F1/26 , G03F1/30 , G03F1/34 , G03F1/36 , G03F1/70 , G03F7/2022 , G03F7/70433 , G03F7/70441 , G03F7/705 , G06F17/5068
摘要： A two mask process for small dimension features on an integrated circuit improves manufacturability and design tolerance. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.
摘要翻译：集成电路上的小尺寸特征的两个掩模过程提高了可制造性和设计容差。第一掩模是不透明场相移掩模，第二掩模是单相结构掩模。使用不透明场上的相移重叠区域将相移窗与不透明场对准。相移掩模主要限定需要相移的区域。单相结构掩模主要限定不需要相移的区域。单相结构掩模还防止相移区域的擦除，并且防止产生否则将由相移掩模产生的不期望的伪影区域。

10. 发明授权

US06818385B2 Phase shifting circuit manufacture method and apparatus 有权
标题翻译：相移电路制造方法及装置
公开(公告)号：US06818385B2
公开(公告)日：2004-11-16
申请号：US10341290
申请日：2003-01-13
申请人： Yao-Ting Wang , Yagyensh C. Pati
发明人： Yao-Ting Wang , Yagyensh C. Pati
IPC分类号： G03F900
CPC分类号： G03F7/70283 , G03F1/26 , G03F1/30 , G03F1/34 , G03F1/36 , G03F1/70 , G03F7/2022 , G03F7/70433 , G03F7/70441 , G03F7/705 , G06F17/5068
摘要： A method for manufacturing integrated circuits using opaque field, phase shift masking. One embodiment of the invention includes using a two mask process. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.
摘要翻译：一种使用不透光场，相移屏蔽制造集成电路的方法。本发明的一个实施例包括使用两个掩模过程。第一掩模是不透明场相移掩模，第二掩模是单相结构掩模。使用不透明场上的相移重叠区域将相移窗与不透明场对准。相移掩模主要限定需要相移的区域。单相结构掩模主要限定不需要相移的区域。单相结构掩模还防止相移区域的擦除，并且防止产生否则将由相移掩模产生的不期望的伪影区域。

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