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1. 发明授权

US07989338B2 Grain boundary blocking for stress migration and electromigration improvement in CU interconnects 有权
标题翻译：用于CU互连中的应力迁移和电迁移改进的谷物边界阻塞
公开(公告)号：US07989338B2
公开(公告)日：2011-08-02
申请号：US11153747
申请日：2005-06-15
申请人： Fan Zhang , Kho Liep Chok , Alex See , Cheng-Cheh Tan , Xiaomei Bu , Tae Jong Lee , Liang Choo Hsia
发明人： Fan Zhang , Kho Liep Chok , Alex See , Cheng-Cheh Tan , Xiaomei Bu , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L21/76859 , H01L21/76856 , H01L21/76864
摘要： Example embodiments of a structure and method for forming a copper interconnect having a doped region near a top surface. The doped region has implanted alloying elements that block grain boundaries and reduce stress and electro migration. In a first example embodiment, the barrier layer is left over the inter metal dielectric layer during the alloying element implant. The barrier layer is later removed with a planarization process. In a second example embodiment the barrier layer is removed before the alloying element implant and a hard mask blocks the alloying element from being implanted in the inter metal dielectric layer.
摘要翻译：用于形成具有在顶表面附近的掺杂区域的铜互连的结构和方法的示例实施例。掺杂区域已经植入了阻挡晶界并减少应力和电迁移的合金元素。在第一示例性实施例中，在合金元素植入期间，阻挡层留在金属间介电层上。稍后通过平坦化处理去除阻挡层。在第二示例性实施例中，在合金元素注入之前去除阻挡层，并且硬掩模阻止合金元素被注入在金属间介电层中。

2. 发明授权

US07224060B2 Integrated circuit with protective moat 有权
标题翻译：集成电路与防护护城河
公开(公告)号：US07224060B2
公开(公告)日：2007-05-29
申请号：US10768796
申请日：2004-01-30
申请人： Fan Zhang , Kho Liep Chok , Tae Jong Lee , Xiaomei Bu , Meng Luo , Chian Yuh Sin , Yee Mei Foong , Luona Goh , Liang Choo Hsia , Huey Ming Chong
发明人： Fan Zhang , Kho Liep Chok , Tae Jong Lee , Xiaomei Bu , Meng Luo , Chian Yuh Sin , Yee Mei Foong , Luona Goh , Liang Choo Hsia , Huey Ming Chong
IPC分类号： H01L23/04
CPC分类号： H01L23/585 , H01L23/3192 , H01L2924/0002 , H01L2924/3025 , H01L2924/00
摘要： A method of manufacturing an integrated circuit provides a substrate having a semiconductor device, and includes forming an intermetal dielectric layer over the substrate and the semiconductor device. A metal wire is formed above the semiconductor device and in contact therewith and a passivation layer is formed over the intermetal dielectric layer. A bond pad is formed connected to the metal wire. A protective moat, with sidewall passivation layer, is formed through the passivation layer and the intermetal dielectric layer, and is located between the metal wire and an outside edge of the integrated circuit.
摘要翻译：制造集成电路的方法提供了具有半导体器件的衬底，并且包括在衬底和半导体器件上形成金属间电介质层。金属线形成在半导体器件的上方并与之接触，并且在金属间电介质层之上形成钝化层。形成与金属线连接的接合焊盘。通过钝化层和金属间电介质层形成具有侧壁钝化层的保护护套，并且位于金属线和集成电路的外边缘之间。

3. 发明申请

US20070293039A1 Combined copper plating method to improve gap fill 有权
标题翻译：组合镀铜方法提高间隙填充
公开(公告)号：US20070293039A1
公开(公告)日：2007-12-20
申请号：US11454397
申请日：2006-06-16
申请人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
发明人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/4763 , H01L21/44
CPC分类号： H01L21/288 , H01L21/2885 , H01L21/76873 , H01L21/76877
摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.
摘要翻译：公开了一种在电介质层中填充间隙的方法。提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。然后使用ECP来完成间隙的铜填充。对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

4. 发明授权

US07585768B2 Combined copper plating method to improve gap fill 有权
标题翻译：组合镀铜方法提高间隙填充
公开(公告)号：US07585768B2
公开(公告)日：2009-09-08
申请号：US11454397
申请日：2006-06-16
申请人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
发明人： Xiaomei Bu , Alex See , Fan Zhang , Jane Hui , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/44
CPC分类号： H01L21/288 , H01L21/2885 , H01L21/76873 , H01L21/76877
摘要： A method of filling gaps in dielectric layers is disclosed. A wafer is provided having a dielectric layer containing gaps to be filled with copper, some of the gaps, denoted deeper gaps, having aspect ratios so large that filling these gaps with copper using ECP could result in pinhole like voids. A blanket conformal metal barrier layer is formed and the wafer is then submerged in a solution to electroless plate a blanket conformal copper seed layer. A partial filling of deeper gaps with copper reduces the effective aspect ratios of the deeper gaps to the extent that ECP could be used to complete the copper filling of the gaps without forming pinhole like voids. ECP is then used to complete the copper filling of the gaps. The wafer is annealed and CMP performed to planarize the surface, giving rise to a structure in which the gaps are filled with copper and are separated by the dielectric layer.
摘要翻译：公开了一种在电介质层中填充间隙的方法。提供具有包含要填充铜的间隙的电介质层的晶片，其中一些间隙表示为更深的间隙，其纵横比大到使用ECP填充这些间隙的铜可导致针孔状空隙。形成覆盖的共形金属阻挡层，然后将晶片浸没在无电镀平板上的覆盖层保形铜种子层的溶液中。用铜部分填充更深的间隙可以减少较深间隙的有效纵横比，使得ECP可以用于完成间隙的铜填充而不形成针孔如空隙的程度。然后使用ECP来完成间隙的铜填充。对晶片进行退火并进行CMP以平坦化表面，产生其中间隙被铜填充并由介电层分离的结构。

5. 发明授权

US07094669B2 Structure and method of liner air gap formation 有权
公开(公告)号：US07094669B2
公开(公告)日：2006-08-22
申请号：US10910499
申请日：2004-08-03
申请人： Xiaomei Bu , Alex See , Tae Jong Lee , Fan Zhang , Yeon Kheng Lim , Liang Choo Hsia
发明人： Xiaomei Bu , Alex See , Tae Jong Lee , Fan Zhang , Yeon Kheng Lim , Liang Choo Hsia
IPC分类号： H01L21/46 , H01L21/78 , H01L21/301 , H01L21/76 , H01L21/4763
CPC分类号： H01L21/7682 , H01L21/76807 , H01L21/76831 , H01L23/5222 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A structure and method of a semiconductor device with liner air gaps next to interconnects and dielectric layers. A dielectric layer is formed over a lower dielectric layer and a lower interconnect over a substrate. We form an interconnect opening in the dielectric layer. The opening has sidewalls of the dielectric layer. A sacrificial liner is formed over the sidewalls of the interconnect opening. An upper interconnect is formed that fills the opening. We remove the sacrificial liner/spacers to form (air) liner gaps.

6. 发明授权

US07276440B2 Method of fabrication of a die oxide ring 有权
标题翻译：芯片氧化物环的制造方法
公开(公告)号：US07276440B2
公开(公告)日：2007-10-02
申请号：US10734423
申请日：2003-12-12
申请人： Fan Zhang , Bei Chao Zhang , Wuping Liu , Kho Liep Chok , Liang Choo Hsia , Tae Jong Lee , Juan Boon Tan , Xian Bin Wang
发明人： Fan Zhang , Bei Chao Zhang , Wuping Liu , Kho Liep Chok , Liang Choo Hsia , Tae Jong Lee , Juan Boon Tan , Xian Bin Wang
IPC分类号： H01L23/04
CPC分类号： H01L23/562 , H01L23/3178 , H01L2924/0002 , H01L2924/09701 , H01L2924/00
摘要： In accordance with the objectives of the invention a new design and method for the implementation thereof is provided in the form of an “oxide ring”. A conventional die is provided with a guard ring or sealing ring, which surrounds and isolates the active surface area of an individual semiconductor die. The “oxide ring” of the invention surrounds the guard ring or sealing ring and forms in this manner a mechanical stress release buffer between the sawing paths of the die and the active surface area of the singulated individual semiconductor die.
摘要翻译：根据本发明的目的，以“氧化物环”的形式提供了一种用于实施本发明的新设计和方法。传统的模具设置有保护环或密封环，其围绕并隔离单个半导体管芯的有源表面积。本发明的“氧化物环”围绕保护环或密封环，并以这种方式形成在管芯的锯切路径和单个化的半导体管芯的有源表面区域之间的机械应力释放缓冲器。

7. 发明授权

US08598031B2 Reliable interconnect for semiconductor device 有权
公开(公告)号：US08598031B2
公开(公告)日：2013-12-03
申请号：US12568658
申请日：2009-09-28
申请人： Fan Zhang , Xiaomei Bu , Jane Hui , Tae Jong Lee , Liang Choo Hsia
发明人： Fan Zhang , Xiaomei Bu , Jane Hui , Tae Jong Lee , Liang Choo Hsia
IPC分类号： H01L21/4763
CPC分类号： H01L23/5226 , H01L21/31127 , H01L21/31144 , H01L21/3212 , H01L21/76822 , H01L21/7684 , H01L21/76885 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.

8. 发明授权

US09318378B2 Slot designs in wide metal lines 有权
公开(公告)号：US09318378B2
公开(公告)日：2016-04-19
申请号：US10923123
申请日：2004-08-21
申请人： Yeow Kheng Lim , Alex See , Tae Jong Lee , David Vigar , Liang Choo Hsia , Kin Leong Pey
发明人： Yeow Kheng Lim , Alex See , Tae Jong Lee , David Vigar , Liang Choo Hsia , Kin Leong Pey
IPC分类号： H01L21/76 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L23/528 , H01L21/0276 , H01L21/288 , H01L21/3212 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/7685 , H01L21/76879 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

9. 发明授权

US07253097B2 Integrated circuit system using dual damascene process 有权
标题翻译：集成电路系统采用双镶嵌工艺
公开(公告)号：US07253097B2
公开(公告)日：2007-08-07
申请号：US11160624
申请日：2005-06-30
申请人： Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
发明人： Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
IPC分类号： H01L21/4763
CPC分类号： H01L21/76831 , H01L21/76814 , H01L21/76844 , H01L21/76846
摘要： An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.
摘要翻译：集成电路系统包括提供其上设置有半导体器件的半导体衬底。第一电介质层形成在半导体衬底之上，并且第一导体芯形成在第一电介质层中。在第一导体芯上形成停止层。在停止层上形成第二电介质层。在第二电介质层中形成沟道和通孔。第二介质层中的通道和通孔被湿清洗。沉积阻挡金属层以在第二介电层中对通道和通孔进行排列。从电介质层中的通孔的底部选择性地蚀刻阻挡金属层，并且在阻挡金属层上方形成第二导体芯以填充第二通道和通孔，以将第二导体芯连接到第一导体芯。

10. 发明申请

US20070001303A1 INTEGRATED CIRCUIT SYSTEM USING DUAL DAMASCENE PROCESS 有权
标题翻译：集成电路系统使用双重DAMASCENE过程
公开(公告)号：US20070001303A1
公开(公告)日：2007-01-04
申请号：US11160624
申请日：2005-06-30
申请人： Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
发明人： Yeow Kheng Lim , Chim Seng Seet , Tae Jong Lee , Liang-Choo Hsia , Kin Leong Pey
IPC分类号： H01L23/52
CPC分类号： H01L21/76831 , H01L21/76814 , H01L21/76844 , H01L21/76846
摘要： An integrated circuit system includes providing a semiconductor substrate having a semiconductor device provided thereon. A first dielectric layer is formed over the semiconductor substrate, and a first conductor core is formed in the first dielectric layer. A stop layer is formed over the first conductor core. A second dielectric layer is formed over the stop layer. A channel and a via are formed in the second dielectric layer. The channel and the via in the second dielectric layer are wet cleaned. A barrier metal layer is deposited to line the channel and the via in the second dielectric layer. The barrier metal layer is selectively etched from the bottom of the via in the dielectric layer, and a second conductor core is formed over the barrier metal layer to fill the second channel and the via to connect the second conductor core to the first conductor core.
摘要翻译：集成电路系统包括提供其上设置有半导体器件的半导体衬底。第一电介质层形成在半导体衬底之上，并且第一导体芯形成在第一电介质层中。在第一导体芯上形成停止层。在停止层上形成第二电介质层。在第二电介质层中形成沟道和通孔。第二介质层中的通道和通孔被湿清洗。沉积阻挡金属层以在第二介电层中对通道和通孔进行排列。从电介质层中的通孔的底部选择性地蚀刻阻挡金属层，并且在阻挡金属层上方形成第二导体芯以填充第二通道和通孔，以将第二导体芯连接到第一导体芯。

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