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1. 发明授权

US09318378B2 Slot designs in wide metal lines 有权
公开(公告)号：US09318378B2
公开(公告)日：2016-04-19
申请号：US10923123
申请日：2004-08-21
申请人： Yeow Kheng Lim , Alex See , Tae Jong Lee , David Vigar , Liang Choo Hsia , Kin Leong Pey
发明人： Yeow Kheng Lim , Alex See , Tae Jong Lee , David Vigar , Liang Choo Hsia , Kin Leong Pey
IPC分类号： H01L21/76 , H01L21/768 , H01L23/522 , H01L23/528 , H01L23/532
CPC分类号： H01L23/528 , H01L21/0276 , H01L21/288 , H01L21/3212 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/7685 , H01L21/76879 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

2. 发明申请

US20060040491A1 Slot designs in wide metal lines 有权
标题翻译：狭槽金属线槽设计
公开(公告)号：US20060040491A1
公开(公告)日：2006-02-23
申请号：US10923123
申请日：2004-08-21
申请人： Yeow Lim , Alex See , Tae Lee , David Vigar , Liang Hsia , Kin Pey
发明人： Yeow Lim , Alex See , Tae Lee , David Vigar , Liang Hsia , Kin Pey
IPC分类号： H01L21/4763
CPC分类号： H01L23/528 , H01L21/0276 , H01L21/288 , H01L21/3212 , H01L21/76802 , H01L21/76808 , H01L21/76816 , H01L21/7684 , H01L21/76843 , H01L21/7685 , H01L21/76879 , H01L23/5226 , H01L23/53228 , H01L23/53295 , H01L23/562 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.
摘要翻译：用于宽线槽以减少压力的方法和结构。一种示例性实施例的方法和结构是一种互连结构，包括：包括宽线的互连。宽线有第一个插槽。第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。通孔插头可以从上方或下方接触宽线。另一个示例性实施例是双镶嵌互连结构，包括：双镶嵌形互连件，其包括通孔塞，第一槽和宽线。宽线有第一个插槽。第一槽与通孔塞隔开第一距离，使得第一槽减轻宽线和通孔塞上的应力。

3. 发明申请

US20100308415A1 ANALOGUE THIN-OXIDE MOSFET 审中-公开
标题翻译：模拟氧化物MOSFET
公开(公告)号：US20100308415A1
公开(公告)日：2010-12-09
申请号：US12783215
申请日：2010-05-19
申请人： Rainer Herberholz , David Vigar , Sean Minehane , Mark Redford
发明人： Rainer Herberholz , David Vigar , Sean Minehane , Mark Redford
IPC分类号： H01L27/092 , H01L21/8238 , G06F17/50 , B05C11/00
CPC分类号： H01L21/823857 , H01L27/0922
摘要： A dual gate oxide CMOS technology providing three types of transistor; a thin oxide device, a thick oxide device, and a thin oxide device using the implant type of the thick oxide device for providing improved analogue performance.
摘要翻译：提供三种晶体管的双栅极氧化CMOS技术; 薄氧化物装置，厚氧化物装置和使用注入类型的厚氧化物装置的薄氧化物装置，用于提供改进的模拟性能。

4. 发明申请

US20050059194A1 Method of forming double-gated silicon-on-insulator (SOI) transistors with corner rounding 有权
公开(公告)号：US20050059194A1
公开(公告)日：2005-03-17
申请号：US10662674
申请日：2003-09-15
申请人： Yong Lee , Da Jin , David Vigar
发明人： Yong Lee , Da Jin , David Vigar
IPC分类号： H01L21/00 , H01L21/336 , H01L21/84 , H01L29/423 , H01L29/786
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/7854 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.

5. 发明授权

US06787404B1 Method of forming double-gated silicon-on-insulator (SOI) transistors with reduced gate to source-drain overlap capacitance 有权
标题翻译：形成具有降低的栅 - 源 - 重叠电容的双栅绝缘体（SOI）晶体管的方法
公开(公告)号：US06787404B1
公开(公告)日：2004-09-07
申请号：US10664262
申请日：2003-09-17
申请人： Yong Meng Lee , Da Jin , David Vigar
发明人： Yong Meng Lee , Da Jin , David Vigar
IPC分类号： H01L2100
CPC分类号： H01L29/66772 , H01L29/42384 , H01L29/42392 , H01L29/4908 , H01L29/66553 , H01L29/78648
摘要： A method of forming a double-gated transistor comprising the following sequential steps. A substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned SOI silicon layer including a source region and a drain region connected by a channel portion. An encasing oxide layer is formed over the patterned SOI silicon layer to form an encased patterned SOI silicon layer. A patterned dummy layer is formed over the encased patterned SOI silicon layer. The patterned dummy layer having an opening, with exposed side walls, exposing: the channel portion of the encased patterned SOI silicon layer; and portions of the upper surface of the SOI oxide layer. Offset spacers are over the exposed side walls of the patterned dummy layer opening. The SOI oxide layer is etched while minimizing the undercut portions of the upper surface of the SOI oxide layer are undercut into the SOI oxide layer to form a minimal undercut. The minimizing undercutting process also removing the offset spacers and the encasing oxide layer over the channel portion of the patterned SOI silicon layer. A conformal oxide layer is formed around the channel portion of the patterned SOI silicon layer. A gate is formed within the patterned dummy layer opening. The gate including an upper gate above the patterned SOI silicon layer and a lower gate under the patterned SOI silicon layer. The patterned dummy layer is then removed to form the double-gated transistor.
摘要翻译：一种形成双门控晶体管的方法，包括以下顺序步骤。提供了具有形成在其上的SOI结构的衬底。 SOI结构包括下部SOI氧化物层和上部SOI硅层。图案化SOI硅层以形成图案化SOI硅层，其包括通过沟道部分连接的源极区域和漏极区域。在图案化SOI硅层上形成包围氧化物层，以形成被封装的图案化SOI硅层。在封装的图案化SOI硅层上形成图案化虚拟层。具有开口的图案化虚拟层具有暴露的侧壁，暴露：被封装的图案化SOI硅层的沟道部分; 以及SOI氧化物层的上表面的部分。偏移间隔物在图案化虚拟层开口的暴露的侧壁上方。蚀刻SOI氧化物层，同时最小化SOI氧化物层的上表面的底切部分被切入SOI氧化物层中以形成最小的底切。最小化底切工艺也去除了图案化SOI硅层的通道部分上的偏移间隔物和包围氧化物层。在图案化SOI硅层的沟道部分周围形成保形氧化物层。在图案化虚拟层开口内形成栅极。栅极包括在图案化SOI硅层上方的上栅极和在图案化SOI硅层下方的下栅极。然后去除图案化的虚拟层以形成双门控晶体管。

6. 发明授权

US08658524B2 On-gate contacts in a MOS device 有权
标题翻译： MOS器件中的栅极接点
公开(公告)号：US08658524B2
公开(公告)日：2014-02-25
申请号：US13515758
申请日：2010-12-02
申请人： Rainer Herberholz , David Vigar
发明人： Rainer Herberholz , David Vigar
IPC分类号： H01L21/3205
CPC分类号： H01L23/4824 , H01L2924/0002 , H01L2924/00
摘要： A MOS device, (400) comprising a semiconductor substrate comprising a channel, an electrode (402) insulated from the channel and positioned at least partly over the channel, and at least one contact (403) to the electrode, the at least one contact being positioned at least partly over the channel.
摘要翻译：一种MOS器件（400），包括：包括沟道的半导体衬底，与所述沟道绝缘并且至少部分地位于所述沟道上的电极;以及至少一个接触（403）到所述电极，所述至少一个接触至少部分地位于通道上方。

7. 发明申请

US20110156157A1 ONE-TIME PROGRAMMABLE CHARGE-TRAPPING NON-VOLATILE MEMORY DEVICE 审中-公开
标题翻译：一次可编程充电捕获非易失性存储器件
公开(公告)号：US20110156157A1
公开(公告)日：2011-06-30
申请号：US13045754
申请日：2011-03-11
申请人： Luca Milani , Rainer Herberholz , David Vigar
发明人： Luca Milani , Rainer Herberholz , David Vigar
IPC分类号： H01L27/092 , H01L21/8238 , B05C11/00
CPC分类号： H01L21/823857 , H01L27/0922
摘要： A one-time programmable (OTP) charge-trapping non-volatile memory (NVM) device is described. In an embodiment, an OTP transistor is formed using a thick gate oxide typically used in producing an I/O MOS transistor and source/drain extensions which are highly doped, shallow and include pocket implants and which are typically used in producing a CORE thin-oxide MOS transistor. In an optimization, the OTP transistor may be formed with two narrow active areas instead of one wider active area. This provides increased performance compared to a device with a wider active area and reduced variability compared to a device with one narrow active area. In another embodiment, a dual gate oxide CMOS technology provides three types of transistor; a thin oxide device, a thick oxide device, and a thick oxide device using the implant type of the thin oxide device for providing an OTP charge-trapping NVM device.
摘要翻译：描述了一次性可编程（OTP）电荷捕获非易失性存储器（NVM）器件。在一个实施例中，OTP晶体管使用通常用于制造I / O MOS晶体管的厚栅极氧化物和高掺杂，浅的并包括袋式注入的源极/漏极延伸部，并且通常用于生产CORE薄膜晶体管，氧化物MOS晶体管。在优化中，OTP晶体管可以形成有两个窄的有源区域而不是一个较宽的有源区域。与具有一个窄有效面积的器件相比，与具有更宽的有源面积的器件相比，具有更低的变化性，这提供了更高的性能。在另一个实施例中，双栅极氧化物CMOS技术提供三种类型的晶体管; 薄氧化物装置，厚氧化物装置和厚氧化物装置，其使用注入类型的薄氧化物装置来提供OTP电荷俘获NVM装置。

8. 发明授权

US07141854B2 Double-gated silicon-on-insulator (SOI) transistors with corner rounding 有权
标题翻译：双栅绝缘体（SOI）晶体管，带圆角
公开(公告)号：US07141854B2
公开(公告)日：2006-11-28
申请号：US11174857
申请日：2005-07-05
申请人： Yong Meng Lee , Da Jin , David Vigar
发明人： Yong Meng Lee , Da Jin , David Vigar
IPC分类号： H01L27/01 , H01L27/12 , H01L31/0392 , H01L23/62
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/42392 , H01L29/66772 , H01L29/7854 , H01L29/78648 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a double-gated transistor having a rounded active region to improve GOI and leakage current control comprises the following steps, inter alia. An SOI substrate is patterned and a rounded oxide layer is formed over the exposed side walls of a patterned upper SOI silicon layer. A dummy layer, having an opening defining a gate, is formed over the exposed patterned top oxide layer and the exposed portions of the upper SOI silicon layer. An undercut is formed into the undercut lower SOI oxide layer and the exposed gate area portion of the oxide layer is removed. The portion of the rounded oxide layer within the gate area is removed and a conformal oxide layer is formed over a part of the structure. A gate is formed within the second patterned dummy layer opening and the patterned dummy layer is removed to form the double gated transistor.
摘要翻译：形成具有圆形有源区域以提高GOI和漏电流控制的双门控晶体管的方法尤其包括以下步骤。图案化SOI衬底，并且在图案化的上SOI硅层的暴露侧壁上形成圆形氧化物层。在暴露的图案化的顶部氧化物层和上部SOI硅层的暴露部分之上形成具有限定栅极的开口的虚设层。在底切下面的SOI氧化物层中形成底切，去除氧化物层的暴露的栅极区域部分。去除栅极区域内的圆形氧化物层的部分，并且在该结构的一部分上形成共形氧化物层。在第二图案化虚拟层开口内形成栅极，去除图案化虚拟层以形成双门控晶体管。

9. 发明授权

US08816441B2 Gate depletion drain extended MOS transistor 有权
标题翻译：栅极耗尽漏极扩展MOS晶体管
公开(公告)号：US08816441B2
公开(公告)日：2014-08-26
申请号：US13086560
申请日：2011-04-14
申请人： Rainer Herberholz , Ludovic Oddoart , David Vigar
发明人： Rainer Herberholz , Ludovic Oddoart , David Vigar
IPC分类号： H01L27/088
CPC分类号： H01L21/823418 , H01L21/26586 , H01L21/266 , H01L21/28035 , H01L21/823437 , H01L29/0653 , H01L29/1045 , H01L29/4916 , H01L29/66537 , H01L29/66583 , H01L29/66659 , H01L29/7835
摘要： A drain extended MOS transistor configured to operate in a gate-depletion regime. Devices comprising such transistors are described together with fabrication processes for such devices and transistors.
摘要翻译：漏极扩展MOS晶体管被配置为以栅极耗尽方式工作。包括这种晶体管的器件与这种器件和晶体管的制造工艺一起被描述。

10. 发明授权

US07089522B2 Device, design and method for a slot in a conductive area 有权
标题翻译：导电区域插槽的装置，设计和方法
公开(公告)号：US07089522B2
公开(公告)日：2006-08-08
申请号：US10458992
申请日：2003-06-11
申请人： Patrick Tan , Kheng Chok Tee , David Vigar , Tat Wei Chua
发明人： Patrick Tan , Kheng Chok Tee , David Vigar , Tat Wei Chua
IPC分类号： G06F17/50
CPC分类号： G06F17/5068 , H01L21/7684 , H01L23/528 , H01L2924/0002 , H01L2924/00
摘要： A design, device, system and process for placing slots in active regions (e.g., metal areas). Embodiments of the present invention improve the planarization of metal areas (e.g., lines) and insulators by reducing depressions (e.g., dishing) in the metal areas by including symmetric or square slots inside selected wide metal lines, by adhering to a set of placement rules. Embodiments reduce dishing in copper dual damascene structures. Embodiments reduce data processing requirements for designing and arranging the layout of IC devices and the slots.
摘要翻译：用于在有源区域（例如，金属区域）中放置槽的设计，装置，系统和工艺。本发明的实施例通过通过在选定的宽金属线内包括对称或方形槽来减少金属区域中的凹陷（例如，凹陷）来改善金属区域（例如，线）和绝缘体的平坦化，通过遵守一组放置规则。实施例减少铜双镶嵌结构中的凹陷。实施例减少了用于设计和布置IC器件和插槽布局的数据处理要求。

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