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1. 发明授权

US07971034B2 Reduced overhead address mode change management in a pipelined, recycling microprocessor 失效
标题翻译：在流水线回收微处理器中减少开销地址模式更改管理
公开(公告)号：US07971034B2
公开(公告)日：2011-06-28
申请号：US12051415
申请日：2008-03-19
申请人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, Jr. , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, Jr. , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F9/00 , G06F9/44 , G06F9/30
CPC分类号： G06F9/30189 , G06F9/30076 , G06F9/342 , G06F9/3802 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F9/3867
摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.
摘要翻译：提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。回收微处理器包括在其上执行的逻辑。微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

2. 发明申请

US20090240929A1 METHOD, SYSTEM AND COMPUTER PROGRAM PRODUCT FOR REDUCED OVERHEAD ADDRESS MODE CHANGE MANAGEMENT IN A PIPELINED, RECYLING MICROPROCESSOR 失效
标题翻译：方法，系统和计算机程序产品，用于在管道，回收微处理器中减少地址模式更改管理
公开(公告)号：US20090240929A1
公开(公告)日：2009-09-24
申请号：US12051415
申请日：2008-03-19
申请人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, JR. , Chung-Lung Kevin Shum , Charles F. Webb
发明人： David S. Hutton , Michael Billeci , Fadi Y. Busaba , Brian R. Prasky , John G. Rell, JR. , Chung-Lung Kevin Shum , Charles F. Webb
IPC分类号： G06F9/312
CPC分类号： G06F9/30189 , G06F9/30076 , G06F9/342 , G06F9/3802 , G06F9/3824 , G06F9/3836 , G06F9/3861 , G06F9/3867
摘要： A method, system, and computer program product for reduced overhead address mode change management in a pipelined, recycling microprocessor are provided. The recycling microprocessor includes logic executing thereon. The microprocessor also includes an instruction fetch unit (IFU) supporting computation of address adds in selected address modes and reporting non-equal comparison of the computation to the logic. The microprocessor further includes a fixed point unit determining whether the mode has changed and reporting changes to the logic. Upon determining the comparison yields an equal result but the mode has changed, a recycle event is triggered to ensure subsequent ofetches are relaunched in the correct mode and that no execution writebacks occur from work performed in an incorrect mode. For comparisons yielding a non-equal result and a changed mode, the logic clears bits set in response to the determinations, and a serialization event is taken to reset a corresponding pipeline for operation in the correct mode.
摘要翻译：提供了一种用于在流水线式回收微处理器中减少开销地址模式改变管理的方法，系统和计算机程序产品。回收微处理器包括在其上执行的逻辑。微处理器还包括一个指令提取单元（IFU），用于支持在所选择的地址模式中添加的地址的计算，并且将该计算的不相等的比较报告给逻辑。微处理器还包括确定模式是否改变并且对逻辑进行报告改变的固定点单元。在确定比较时，产生相等的结果，但是模式已经改变，触发一个循环事件，以确保以正确的模式重新启动后续的提取，并且在不正确的模式下执行的工作不会执行执行回写。为了比较产生不相等的结果和改变的模式，逻辑清除响应于确定的位设置，并且采用串行化事件来复位相应的流水线以便以正确的模式进行操作。

3. 发明申请

US20090210775A1 METHOD AND SYSTEM FOR INSTRUCTION ADDRESS PARITY COMPARISON 有权
标题翻译：方法和系统的指令地址的比较
公开(公告)号：US20090210775A1
公开(公告)日：2009-08-20
申请号：US12031732
申请日：2008-02-15
申请人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
发明人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
IPC分类号： G06F11/00
CPC分类号： G06F11/10
摘要： A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing circuitry. The method also includes receiving the distributed instruction address parity value from the one or more functional units, and calculating a completing instruction address (CIA) parity value associated with completing the instruction. The method further includes generating an error indicator in response to a mismatch between the received instruction address parity value and the CIA parity value.
摘要翻译：提供了一种用于指令地址奇偶校验比较的方法和系统。该方法包括计算指令的指令地址奇偶校验值，并将指令地址奇偶校验值分配给处理电路中的一个或多个功能单元。该方法还包括从一个或多个功能单元接收分布式指令地址奇偶校验值，以及计算与完成指令相关联的完成指令地址（CIA）奇偶校验值。该方法还包括响应于接收到的指令地址奇偶校验值和CIA奇偶校验值之间的不匹配而产生错误指示符。

4. 发明授权

US08140951B2 Method and system for instruction address parity comparison 有权
标题翻译：指令地址奇偶校验比较方法和系统
公开(公告)号：US08140951B2
公开(公告)日：2012-03-20
申请号：US12031732
申请日：2008-02-15
申请人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
发明人： Fadi Y. Busaba , Brian R. Prasky , Chung-Lung Kevin Shum
IPC分类号： G06F11/00 , H03M13/00
CPC分类号： G06F11/10
摘要： A method and system for instruction address parity comparison are provided. The method includes calculating an instruction address parity value for an instruction, and distributing the instruction address parity value to one or more functional units in processing circuitry. The method also includes receiving the distributed instruction address parity value from the one or more functional units, and calculating a completing instruction address (CIA) parity value associated with completing the instruction. The method further includes generating an error indicator in response to a mismatch between the received instruction address parity value and the CIA parity value.
摘要翻译：提供了一种用于指令地址奇偶校验比较的方法和系统。该方法包括计算指令的指令地址奇偶校验值，并将指令地址奇偶校验值分配给处理电路中的一个或多个功能单元。该方法还包括从一个或多个功能单元接收分布式指令地址奇偶校验值，以及计算与完成指令相关联的完成指令地址（CIA）奇偶校验值。该方法还包括响应于接收到的指令地址奇偶校验值和CIA奇偶校验值之间的不匹配而产生错误指示符。

5. 发明授权

US08930950B2 Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors 有权
标题翻译：在计算环境中迁移线程的管理，以将多个线程模式处理器转换为单线程模式处理器
公开(公告)号：US08930950B2
公开(公告)日：2015-01-06
申请号：US13353550
申请日：2012-01-19
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/46 , G06F9/48 , G06F9/50
CPC分类号： G06F9/4856 , G06F9/505 , G06F9/5088
摘要： Threads of a computing environment are managed to improve system performance. Threads are migrated between processors to take advantage of single thread processing mode, when possible. As an example, inactive threads are migrated from one or more processors, potentially freeing-up one or more processors to execute an active thread. Active threads are migrated from one processor to another to transform multiple threading mode processors to single thread mode processors.
摘要翻译：管理计算环境的线程以提高系统性能。线程在处理器之间迁移，以尽可能利用单线程处理模式。作为示例，非活动线程从一个或多个处理器迁移，潜在地释放一个或多个处理器以执行活动线程。活动线程从一个处理器迁移到另一个处理器，以将多个线程模式处理器转换为单线程模式处理器。

6. 发明授权

US08806139B2 Cache set replacement order based on temporal set recording 有权
标题翻译：基于时间设置记录的缓存集替换顺序
公开(公告)号：US08806139B2
公开(公告)日：2014-08-12
申请号：US13354894
申请日：2012-01-20
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F12/12
CPC分类号： G06F12/0875 , G06F12/126
摘要： A technique is provided for cache management of a cache. The processing circuit determines a miss count and a hit position field during a previous execution of an instruction requesting that a data element be stored in a cache. The miss count and the hit position field are stored for a data element corresponding to an instruction that requests storage of the data element. The processing circuit places the data element in a hierarchical order based on the miss count and/or the hit position field. The hit position field includes a hierarchical position related to the data element in the cache.
摘要翻译：提供了用于高速缓存的高速缓存管理的技术。处理电路在先前执行请求数据元素存储在高速缓存中的指令期间确定未命中和命中位置字段。针对与请求存储数据元素的指令相对应的数据元素存储未命中和命中位置字段。处理电路基于错过次数和/或命中位置字段将数据元素放置成分层次序。命中位置字段包括与缓存中的数据元素相关的分层位置。

7. 发明申请

US20130191832A1 MANAGEMENT OF THREADS WITHIN A COMPUTING ENVIRONMENT 有权
标题翻译：在计算环境中管理螺纹
公开(公告)号：US20130191832A1
公开(公告)日：2013-07-25
申请号：US13353550
申请日：2012-01-19
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/46
CPC分类号： G06F9/4856 , G06F9/505 , G06F9/5088
摘要： Threads of a computing environment are managed to improve system performance. Threads are migrated between processors to take advantage of single thread processing mode, when possible. As an example, inactive threads are migrated from one or more processors, potentially freeing-up one or more processors to execute an active thread. Active threads are migrated from one processor to another to transform multiple threading mode processors to single thread mode processors.
摘要翻译：管理计算环境的线程以提高系统性能。线程在处理器之间迁移，以尽可能利用单线程处理模式。作为示例，非活动线程从一个或多个处理器迁移，潜在地释放一个或多个处理器以执行活动线程。活动线程从一个处理器迁移到另一个处理器，以将多个线程模式处理器转换为单线程模式处理器。

8. 发明授权

US09152510B2 Hardware recovery in multi-threaded processor 有权
公开(公告)号：US09152510B2
公开(公告)日：2015-10-06
申请号：US13548448
申请日：2012-07-13
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/00 , G06F11/14
CPC分类号： G06F11/1479 , G06F11/1438
摘要： A computer system includes a simultaneous multi-threading processor and memory in operable communication with the processor. The processor is configured to perform a method including running multiple threads simultaneously, detecting a hardware error in one or more hardware structures of the processing circuit, and identifying one or more victim threads of the multiple threads. The processor is further configured to identify a plurality of hardware structures associated with execution of the one or more victim threads, isolate the one or more victim threads from the rest of the multiple threads by preventing access to the plurality of hardware structures by the multiple threads, flush the one or more victim threads by resetting hardware states of the plurality of hardware structures, and restore the one or more victim threads by restoring the plurality of hardware structures to a known safe state.

9. 发明申请

US20130332670A1 PROCESS IDENTIFIER-BASED CACHE DATA TRANSFER 有权
标题翻译：基于过程识别器的高速缓存数据传输
公开(公告)号：US20130332670A1
公开(公告)日：2013-12-12
申请号：US13493636
申请日：2012-06-11
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F12/08
CPC分类号： G06F17/30982 , G06F12/0817 , G06F12/12
摘要： Embodiments of the invention relate to process identifier (PID) based cache information transfer. An aspect of the invention includes sending, by a first core of a processor, a PID associated with a cache miss in a first local cache of the first core to a second cache of the processor. Another aspect of the invention includes determining that the PID associated with the cache miss is listed in a PID table of the second cache. Yet another aspect of the invention includes based on the PID being listed in the PID table of the second cache, determining a plurality of entries in a cache directory of the second cache that are associated with the PID. Yet another aspect of the invention includes pushing cache information associated with each of the determined plurality of entries in the cache directory from the second cache to the first local cache.
摘要翻译：本发明的实施例涉及基于过程标识符（PID）的高速缓存信息传送。本发明的一个方面包括由处理器的第一核心将与第一核心的第一本地高速缓存中的高速缓存未命中相关联的PID发送到处理器的第二高速缓存。本发明的另一方面包括确定与高速缓存未命中相关联的PID被列在第二高速缓存的PID表中。本发明的另一方面包括基于PID列在第二高速缓存的PID表中，确定与PID相关联的第二高速缓存的高速缓存目录中的多个条目。本发明的另一方面包括将高速缓存目录中的确定的多个条目中的每一个相关联的缓存信息从第二高速缓存推送到第一本地高速缓存。

10. 发明申请

US20130191678A1 IN SITU PROCESSOR RE-CHARACTERIZATION 有权
标题翻译：在现场处理器重新表征
公开(公告)号：US20130191678A1
公开(公告)日：2013-07-25
申请号：US13353544
申请日：2012-01-19
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F1/08
CPC分类号： G06F11/24 , G06F1/206 , G06F1/32 , G06F1/324
摘要： A re-characterization process is provided that adjusts one or more operating parameters of a processor to improve the health (e.g., reduce errors) of the processor. The parameters include voltage and/or clock frequency, as examples. The processor can be an inactive or active processor for which the re-characterization process is performed. It is performed, in one instance, by a hardware controller in real-time.
摘要翻译：提供重新表征处理，其调整处理器的一个或多个操作参数以改善处理器的健康状况（例如，减少错误）。参数包括电压和/或时钟频率，例如。处理器可以是对其执行重新表征处理的非活动或活动处理器。在一个实例中，它由硬件控制器实时执行。

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