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1. 发明授权

US07689741B2 Dual buffer memory system for reducing data transmission time and control method thereof 有权
标题翻译：双缓冲存储器系统，用于减少数据传输时间及其控制方法
公开(公告)号：US07689741B2
公开(公告)日：2010-03-30
申请号：US10940038
申请日：2004-09-13
申请人： Eun-Suk Kang , Jin-Yub Lee
发明人： Eun-Suk Kang , Jin-Yub Lee
IPC分类号： G06F3/00 , G06F12/00
CPC分类号： G11C7/1075
摘要： A dual buffer memory system capable of improving system performance by reducing a data transmission time and a control method thereof are provided. The dual buffer memory system includes a flash memory block and a plurality of buffers. The dual buffer memory system uses a dual buffering scheme in which one buffer among the plurality of buffers interacts with the flash memory block and simultaneously a different buffer among the plurality of buffers interacts with a host. Therefore, it is possible to reduce a data transmission time between the flash memory and the host, thereby improving system performance.
摘要翻译：提供了能够通过减少数据传输时间来提高系统性能的双缓冲存储器系统及其控制方法。双缓冲存储器系统包括闪存块和多个缓冲器。双缓冲存储器系统使用双缓冲方案，其中多个缓冲器中的一个缓冲器与闪存块交互，并且同时多个缓冲器中的不同缓冲器与主机交互。因此，可以减少闪存与主机之间的数据传输时间，从而提高系统性能。

2. 发明申请

US20050060486A1 Dual buffer memory system for reducing data transmission time and control method thereof 有权
标题翻译：双缓冲存储器系统，用于减少数据传输时间及其控制方法
公开(公告)号：US20050060486A1
公开(公告)日：2005-03-17
申请号：US10940038
申请日：2004-09-13
申请人： Eun-Suk Kang , Jin-Yub Lee
发明人： Eun-Suk Kang , Jin-Yub Lee
IPC分类号： G06F12/00 , G06F15/16 , G11C7/10
CPC分类号： G11C7/1075
摘要： A dual buffer memory system capable of improving system performance by reducing a data transmission time and a control method thereof are provided. The dual buffer memory system includes a flash memory block and a plurality of buffers. The dual buffer memory system uses a dual buffering scheme in which one buffer among the plurality of buffers interacts with the flash memory block and simultaneously a different buffer among the plurality of buffers interacts with a host. Therefore, it is possible to reduce a data transmission time between the flash memory and the host, thereby improving system performance.
摘要翻译：提供了能够通过减少数据传输时间来提高系统性能的双缓冲存储器系统及其控制方法。双缓冲存储器系统包括闪存块和多个缓冲器。双缓冲存储器系统使用双缓冲方案，其中多个缓冲器中的一个缓冲器与闪存块交互，并且同时多个缓冲器中的不同缓冲器与主机交互。因此，可以减少闪存与主机之间的数据传输时间，从而提高系统性能。

3. 发明授权

US08301829B2 Flash memory device and flash memory system including buffer memory 有权
标题翻译：闪存设备和闪存系统包括缓冲存储器
公开(公告)号：US08301829B2
公开(公告)日：2012-10-30
申请号：US13108687
申请日：2011-05-16
申请人： Jin-Yub Lee
发明人： Jin-Yub Lee
IPC分类号： G06F12/02
CPC分类号： G06F12/0246 , G06F12/0638 , G06F2212/7203
摘要： A flash memory device includes a flash memory and a buffer memory. The flash memory is divided into a main region and a spare region. The buffer memory is a random access memory and has the same structure as the flash memory. In addition, the flash memory device further includes control means for mapping an address of the flash memory applied from a host so as to divide a structure of the buffer memory into a main region and a spare region and for controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.
摘要翻译：闪存器件包括闪存和缓冲存储器。闪存分为主区域和备用区域。缓冲存储器是随机存取存储器，并且具有与闪存相同的结构。另外，闪存装置还包括控制装置，用于映射从主机应用的闪速存储器的地址，以将缓冲存储器的结构划分成主区域和备用区域，并用于控制闪速存储器和缓冲器用于将缓冲存储器的数据存储在闪速存储器中或用于将闪存的数据存储在缓冲存储器中的存储器。

4. 发明授权

US07908425B2 Method and device for performing cache reading 有权
标题翻译：用于执行高速缓存读取的方法和设备
公开(公告)号：US07908425B2
公开(公告)日：2011-03-15
申请号：US12216003
申请日：2008-06-27
申请人： Jin-Yub Lee , Sang-Won Hwang
发明人： Jin-Yub Lee , Sang-Won Hwang
IPC分类号： G06F12/00 , G06F12/02
CPC分类号： G06F12/0893 , G11C7/1039 , G11C7/1051 , G11C7/106 , G11C16/0483 , G11C16/26 , G11C2207/2245
摘要： In a read method for a memory device, a bit line is set with data in a first memory cell; and the data on the bit line is stored in a register. The data in the register is transferred to a data bus while setting the bit line with data in a second memory cell. In another read method for a memory device, a bit line of a first memory cell is initialized and the bit line is pre-charged with a pre-charge voltage. Data in a memory cell on the bit line is developed, and a register corresponding to the bit line is initialized. The data on the bit line is stored in the register. The data in the register is output externally while performing the initializing, pre-charging, making and initializing to set the bit line with data in a second memory cell.
摘要翻译：在存储器件的读取方法中，位线被设置在第一存储器单元中的数据中; 位线上的数据存储在寄存器中。寄存器中的数据被传送到数据总线，同时在第二个存储单元中将位线设置为数据。在存储器件的另一读取方法中，初始化第一存储器单元的位线，并且利用预充电电压对位线进行预充电。开发位线上存储单元中的数据，初始化与位线对应的寄存器。位线上的数据存储在寄存器中。寄存器中的数据在执行初始化，预充电，制作和初始化时从外部输出，以将位线设置为第二个存储单元中的数据。

5. 发明授权

US07876613B2 Multi-bit flash memory devices having a single latch structure and related programming methods, systems and memory cards 有权
标题翻译：具有单个锁存结构和相关编程方法，系统和存储卡的多位闪存器件
公开(公告)号：US07876613B2
公开(公告)日：2011-01-25
申请号：US12182274
申请日：2008-07-30
申请人： Sang-Chul Kang , Ho-kil Lee , Jin-Yub Lee
发明人： Sang-Chul Kang , Ho-kil Lee , Jin-Yub Lee
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/3454 , G11C2211/5621 , G11C2211/5642
摘要： Multi-bit flash memory devices are provided. The multi-bit flash memory device includes an array of memory cells and a page buffer block including page buffers. Each of the page buffers has a single latch structure and performs a write operation with respect to memory cells according to loaded data. A buffer random access memory (RAM) is configured to store program data provided from an external host device during a multi-bit program operation. Control logic is provided that is configured to control the page buffer block and the buffer RAM so that program data stored in the buffer RAM is reloaded into the page buffer block whenever data programmed before the multi-bit program operation is compared with data to be currently programmed. The control logic is configured to store data to be programmed next in the buffer RAM before the multi-bit program operation is completed.
摘要翻译：提供多位闪存设备。该多位闪存器件包括存储单元阵列和包括页缓冲器的页缓冲块。每个页面缓冲器具有单个锁存结构，并且根据加载的数据对存储器单元执行写入操作。缓冲随机存取存储器（RAM）被配置为在多位程序操作期间存储从外部主机设备提供的程序数据。提供了控制逻辑，其被配置为控制页面缓冲区块和缓冲器RAM，使得存储在缓冲器RAM中的程序数据被重新加载到页面缓冲器块中，每当在多位程序操作之前编程的数据与当前的数据进行比较程序。控制逻辑被配置为在多位程序操作完成之前存储要在缓冲RAM中接下来被编程的数据。

6. 发明授权

US07813184B2 Multi-block memory device erasing methods and related memory devices 有权
标题翻译：多块存储器件擦除方法和相关存储器件
公开(公告)号：US07813184B2
公开(公告)日：2010-10-12
申请号：US11614413
申请日：2006-12-21
申请人： Hoo-Sung Kim , Hyung-Seok Kang , Jin-Yub Lee
发明人： Hoo-Sung Kim , Hyung-Seok Kang , Jin-Yub Lee
IPC分类号： G11C11/00
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/3445
摘要： Methods of performing multi-block erasing operations on a memory device that includes a plurality of memory blocks are provided. Pursuant to these methods, the rate at which a first voltage that is applied to the memory blocks that are to be erased during the multi-block erasing operation rises is controlled based on the number of memory blocks that are to be erased. The memory device may be a flash memory device, and the first voltage may be an erasing voltage that is applied to a substrate of the flash memory device. The rate at which the first voltage rises may be set so that the substrate of the flash memory device reaches the erasing voltage level at approximately the same time regardless of the number of memory blocks that are to be erased.
摘要翻译：提供了在包括多个存储器块的存储器件上执行多块擦除操作的方法。根据这些方法，基于要擦除的存储块的数量来控制施加到在多块擦除操作期间被擦除的存储块的第一电压上升的速率。存储器件可以是闪存器件，并且第一电压可以是施加到闪存器件的衬底的擦除电压。可以设置第一电压上升的速率，使得闪存器件的衬底在大致相同的时间达到擦除电压电平，而与要擦除的存储器块的数量无关。

7. 发明授权

US07586790B2 Flash memory device and refresh method 有权
标题翻译：闪存设备和刷新方式
公开(公告)号：US07586790B2
公开(公告)日：2009-09-08
申请号：US11842995
申请日：2007-08-22
申请人： Jin-Yub Lee
发明人： Jin-Yub Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/349 , G11C16/3495
摘要： A flash memory device is disclosed and includes a memory cell array comprising memory cells arranged in rows and columns, a page buffer circuit having a single latch structure and configured to read data from a selected page in the memory cell array, and a controller controlling the page buffer circuit to detect memory cells having an improper voltage distribution causes by charge leakage within the selected page.
摘要翻译：公开了一种闪速存储器件，包括存储单元阵列，其包括以行和列排列的存储单元，具有单个锁存结构并被配置为从存储单元阵列中的选定页读取数据的页缓冲器电路，以及控制器用于检测具有不正确的电压分布的存储单元的页缓冲电路是由选定页内的电荷泄漏引起的。

8. 发明授权

US07486557B2 Methods/circuits for programming flash memory devices using overlapping bit line setup and word line enable intervals 有权
标题翻译：用于使用重叠位线设置和字线使能间隔编程闪存设备的方法/电路
公开(公告)号：US07486557B2
公开(公告)日：2009-02-03
申请号：US11480236
申请日：2006-06-30
申请人： Jin-Kook Kim , Jin-Yub Lee
发明人： Jin-Kook Kim , Jin-Yub Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C16/0483
摘要： A method of programming a flash memory device includes charging selection lines with a first voltage while applying program data to bit lines to during a bit line setup interval, then activating a block word line to electrically connect the selection lines to corresponding word lines, and then applying a second voltage, greater than the first voltage, to a selected one of the selection lines. Related devices are also disclosed.
摘要翻译：一种对闪速存储器件进行编程的方法包括：在位线建立间隔期间将程序数据应用于位线，然后激活块字线以将选择线电连接到对应的字线，然后将第一电压充电选择线，然后将大于第一电压的第二电压施加到所选择的选择线之一。还公开了相关设备。

9. 发明授权

US07433246B2 Flash memory device capable of storing multi-bit data and single-big data 有权
标题翻译：能够存储多位数据和单大数据的闪存设备
公开(公告)号：US07433246B2
公开(公告)日：2008-10-07
申请号：US11492151
申请日：2006-07-25
申请人： Jin-Yub Lee
发明人： Jin-Yub Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/5621 , G11C16/0483 , G11C2211/5641
摘要： There is provided a flash memory device capable of manipulating multi-bit and single-bit data. The flash memory device can include a memory cell array with a plurality of memory blocks. The flash memory device can also include a judgment circuit for storing multi-bit/single-bit information indicating whether each of the memory blocks is a multi-bit memory block or not, determining whether or not a memory block of an inputted block address is a multi-bit memory block according to the stored multi-bit/single-bit information and outputting an appropriate flag signal. A read/write circuit for selectively performing multi-bit and single-bit read/program operations of the memory block corresponding to the block address is also included, as well as control logic for controlling the read/write circuit such that the read/write circuit can perform multi-bit or single-bit read/program operations based on the flag signal. An error checking and correction (ECC) circuit including a multi-bit ECC unit and a single-bit ECC unit for checking and correcting an error in a data of the read/write circuit can also be included.
摘要翻译：提供了能够操纵多位和单位数据的闪速存储器件。闪存器件可以包括具有多个存储器块的存储单元阵列。闪存装置还可以包括用于存储指示每个存储块是否是多位存储块的多位/单位信息的判断电路，确定输入块地址的存储块是否为根据所存储的多位/单位信息的多位存储器块，并输出适当的标志信号。还包括用于选择性地执行与块地址相对应的存储块的多位和单位读/写操作的读/写电路，以及用于控制读/写电路的控制逻辑，使得读/写电路可以基于标志信号执行多位或单位读/写操作。还可以包括包括用于检查和校正读/写电路的数据中的错误的多位ECC单元和单位ECC单元的错误检查和校正（ECC）电路。

10. 发明授权

US07289387B2 Wordline decoder of non-volatile memory device using HPMOS 失效
标题翻译：使用HPMOS的非易失性存储器件的字线解码器
公开(公告)号：US07289387B2
公开(公告)日：2007-10-30
申请号：US11383064
申请日：2006-05-12
申请人： Ho-Kil Lee , Jin-Yub Lee
发明人： Ho-Kil Lee , Jin-Yub Lee
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C16/0483 , G11C16/08
摘要： A wordline decoder for a non-volatile memory device includes a first inverter to invert a block selection signal into a first inverted result on a first node, a second inverter to invert the signal on the first node into a second inverted result on a second node, a first and a second transistor, each coupled to a power supply, coupled in series between the second node and a third node, a third transistor coupled between the third node and a fourth node having a gate coupled to the third node, a fourth transistor coupled between a high voltage supply and a fifth node having a source coupled to the high voltage supply and a gate coupled to the third node, and a fifth transistor coupled between the fifth node and the third node having a gate coupled to the first node.
摘要翻译：用于非易失性存储器件的字线解码器包括：第一反相器，用于将块选择信号反转到第一节点上的第一反相结果;第二反相器，用于将第一节点上的信号反转为第二节点上的第二反相结果，第一和第二晶体管，每个耦合到电源，串联耦合在第二节点和第三节点之间;第三晶体管，耦合在第三节点和第四节点之间，第四节点具有耦合到第三节点的栅极;第四晶体管，第四晶体管，耦合在高压电源和耦合到高压电源的源极的第五节点和耦合到第三节点的栅极之间的晶体管，以及耦合在第五节点和第三节点之间的第五晶体管，其具有耦合到第一节点。

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