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1. 发明申请

US20090052252A1 METHODS OF APPLYING READ VOLTAGES IN NAND FLASH MEMORY ARRAYS 审中-公开
标题翻译：在NAND闪存阵列中应用读取电压的方法
公开(公告)号：US20090052252A1
公开(公告)日：2009-02-26
申请号：US12254205
申请日：2008-10-20
申请人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
发明人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/0483 , G11C16/26
摘要： Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.
摘要翻译：提供了一种提高闪存阵列的读取干扰特性的方法。根据该方法，在具有串联选择晶体管，多个存储单元和接地选择晶体管的至少一个单元串的闪速存储器阵列中，将第一读取电压施加到连接的串选择线到串选择晶体管的栅极和连接到接地选择晶体管的栅极的接地选择线。将接地电压施加到从存储单元中选择的存储单元的字线。第二读取电压被施加到与串选择晶体管和地选择晶体管相邻的未被选择的存储单元中的存储单元的字线。然后，将第一读取电压施加到未被选择的其他存储单元。第二读取电压低于第一读取电压。

2. 发明授权

US07843736B2 Nonvolatile memory device and read method thereof 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US07843736B2
公开(公告)日：2010-11-30
申请号：US12396937
申请日：2009-03-03
申请人： Hyung-Seok Kang , Eui-Gyu Han , Hoo-Sung Kim
发明人： Hyung-Seok Kang , Eui-Gyu Han , Hoo-Sung Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/28
摘要： Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.
摘要翻译：公开了一种非易失性存储器件的读取方法，其包括执行第一读取操作，其中第一读取电压被施加到所选择的字线。如果在第一读取操作中出现读取失败，则执行第二读取操作，其中低于第一读取电压的第二读取电压被施加到所选择的字线。如果在第二次读取操作中没有出现读取失败，则通过执行编程操作来固化在第一次读取操作时产生的读取失败。

3. 发明授权

US07813184B2 Multi-block memory device erasing methods and related memory devices 有权
标题翻译：多块存储器件擦除方法和相关存储器件
公开(公告)号：US07813184B2
公开(公告)日：2010-10-12
申请号：US11614413
申请日：2006-12-21
申请人： Hoo-Sung Kim , Hyung-Seok Kang , Jin-Yub Lee
发明人： Hoo-Sung Kim , Hyung-Seok Kang , Jin-Yub Lee
IPC分类号： G11C11/00
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/3445
摘要： Methods of performing multi-block erasing operations on a memory device that includes a plurality of memory blocks are provided. Pursuant to these methods, the rate at which a first voltage that is applied to the memory blocks that are to be erased during the multi-block erasing operation rises is controlled based on the number of memory blocks that are to be erased. The memory device may be a flash memory device, and the first voltage may be an erasing voltage that is applied to a substrate of the flash memory device. The rate at which the first voltage rises may be set so that the substrate of the flash memory device reaches the erasing voltage level at approximately the same time regardless of the number of memory blocks that are to be erased.
摘要翻译：提供了在包括多个存储器块的存储器件上执行多块擦除操作的方法。根据这些方法，基于要擦除的存储块的数量来控制施加到在多块擦除操作期间被擦除的存储块的第一电压上升的速率。存储器件可以是闪存器件，并且第一电压可以是施加到闪存器件的衬底的擦除电压。可以设置第一电压上升的速率，使得闪存器件的衬底在大致相同的时间达到擦除电压电平，而与要擦除的存储器块的数量无关。

4. 发明申请

US20090231922A1 Nonvolatile Memory Device and Read Method Thereof 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US20090231922A1
公开(公告)日：2009-09-17
申请号：US12396937
申请日：2009-03-03
申请人： Hyung-Seok Kang , Eui-Gyu Han , Hoo-Sung Kim
发明人： Hyung-Seok Kang , Eui-Gyu Han , Hoo-Sung Kim
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C16/28
摘要： Disclosed is a read method of a non-volatile memory device which includes performing a first read operation in which a first read voltage is applied to a selected word line. If a read fail arises at the first read operation, a second read operation is performed in which a second read voltage lower than the first read voltage is applied to the selected word line. If no read fail arises at the second read operation, the read fail generated at the first read operation is cured by performing a program operation.
摘要翻译：公开了一种非易失性存储器件的读取方法，其包括执行第一读取操作，其中第一读取电压被施加到所选择的字线。如果在第一读取操作中出现读取失败，则执行第二读取操作，其中低于第一读取电压的第二读取电压被施加到所选择的字线。如果在第二次读取操作中没有出现读取失败，则通过执行编程操作来固化在第一次读取操作时产生的读取失败。

5. 发明授权

US07457160B2 Methods of applying read voltages in NAND flash memory arrays 有权
公开(公告)号：US07457160B2
公开(公告)日：2008-11-25
申请号：US11635995
申请日：2006-12-08
申请人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
发明人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/26
摘要： Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.

6. 发明申请

US20080074931A1 MULTI-BLOCK MEMORY DEVICE ERASING METHODS AND RELATED MEMORY DEVICES 有权
标题翻译：多存储器件擦除方法和相关存储器件
公开(公告)号：US20080074931A1
公开(公告)日：2008-03-27
申请号：US11614413
申请日：2006-12-21
申请人： Hoo-Sung Kim , Hyung-Seok Kang , Jin-Yub Lee
发明人： Hoo-Sung Kim , Hyung-Seok Kang , Jin-Yub Lee
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/3445
摘要： Methods of performing multi-block erasing operations on a memory device that includes a plurality of memory blocks are provided. Pursuant to these methods, the rate at which a first voltage that is applied to the memory blocks that are to be erased during the multi-block erasing operation rises is controlled based on the number of memory blocks that are to be erased. The memory device may be a flash memory device, and the first voltage may be an erasing voltage that is applied to a substrate of the flash memory device. The rate at which the first voltage rises may be set so that the substrate of the flash memory device reaches the erasing voltage level at approximately the same time regardless of the number of memory blocks that are to be erased.
摘要翻译：提供了在包括多个存储器块的存储器件上执行多块擦除操作的方法。根据这些方法，基于要擦除的存储块的数量来控制施加到在多块擦除操作期间被擦除的存储块的第一电压上升的速率。存储器件可以是闪存器件，并且第一电压可以是施加到闪存器件的衬底的擦除电压。可以设置第一电压上升的速率，使得闪存器件的衬底在大致相同的时间达到擦除电压电平，而与要擦除的存储器块的数量无关。

7. 发明授权

US06569528B2 Amphiphilic biodegradable block copolymers and self-assembled polymer aggregates formed from the same in aqueous milieu 失效
公开(公告)号：US06569528B2
公开(公告)日：2003-05-27
申请号：US10173728
申请日：2002-06-19
申请人： Yoon Sung Nam , Hyung Seok Kang , Sang Hoon Han , Ih Seop Chang
发明人： Yoon Sung Nam , Hyung Seok Kang , Sang Hoon Han , Ih Seop Chang
IPC分类号： B32B1502
CPC分类号： A61K9/5153 , A61K9/1075 , A61K47/34 , C08G73/02 , C08G81/00 , C08L53/00 , Y10T428/2982 , C08L2666/02
摘要： There are provided amphiphilic biodegradable block copolymers comprising polyethylenimine (PEI) as a hydrophilic block and aliphatic polyesters as a hydrophobic block, which can form various size of polymer aggregates and have very low critical micelle concentration, approximately 10−3 g/l in comparison with low-molecular-weight micelle, and self-assembled polymer aggregates formed from the block copolymers in aqueous milieu, which can be applied to solubilization of insoluble drug and a delivery system of proteins, genes or drugs.

8. 发明申请

US20080101122A1 Methods of applying read voltages in NAND flash memory arrays 有权
标题翻译：在NAND闪存阵列中应用读取电压的方法
公开(公告)号：US20080101122A1
公开(公告)日：2008-05-01
申请号：US11635995
申请日：2006-12-08
申请人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
发明人： Hyung-seok Kang , Eui-gyu Han , Gyeong-soo Han , Jin-yub Lee , Hoo-sung Kim
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/26
摘要： Provided is a method of improving the read disturb characteristics of a flash memory array. According to the method, in a flash memory array having at least one cell string in which a string selection transistor, a plurality of memory cells, and a ground selection transistor are connected in series, first read voltage is applied to a string selection line connected to a gate of the string selection transistor and a ground selection line connected to a gate of the ground selection transistor. Ground voltage is applied to a word line of a memory cell selected from among the memory cells. Second read voltage is applied to word lines of memory cells, from among the memory cells that are not selected, which are adjacent to the string selection transistor and the ground selection transistor. Then, the first read voltage is applied to the other memory cells that are not selected. The second read voltage is lower than the first read voltage.
摘要翻译：提供了一种提高闪存阵列的读取干扰特性的方法。根据该方法，在具有串联选择晶体管，多个存储单元和接地选择晶体管的至少一个单元串的闪速存储器阵列中，将第一读取电压施加到连接的串选择线到串选择晶体管的栅极和连接到接地选择晶体管的栅极的接地选择线。将接地电压施加到从存储单元中选择的存储单元的字线。第二读取电压被施加到与串选择晶体管和地选择晶体管相邻的未被选择的存储单元中的存储单元的字线。然后，将第一读取电压施加到未被选择的其他存储单元。第二读取电压低于第一读取电压。

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