专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07679408B2 Glitchless clock multiplexer optimized for synchronous and asynchronous clocks 失效
标题翻译：针对同步和异步时钟优化的无毛刺时钟复用器
公开(公告)号：US07679408B2
公开(公告)日：2010-03-16
申请号：US11960832
申请日：2007-12-20
申请人： Eskinder Hailu , Takeo Yasuda
发明人： Eskinder Hailu , Takeo Yasuda
IPC分类号： G06F1/08
CPC分类号： H03K17/005 , G06F1/08
摘要： A circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The circuit comprises an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal. Switching latency is the period in which no clock pulse appears at the final output of the circuit.
摘要翻译：用于使用针对同步和异步时钟优化的无毛刺时钟复用器的逻辑器件来切换时钟信号的电路。该电路包括异步时钟组和一个或多个同步时钟组。异步组包括用于异步时钟源的多个高频无毛刺控制（HFGC）块。每个同步组包括用于同步时钟源的多个HFGC块。该电路包括用于从用于异步时钟源的HFGC块和用于同步时钟源的HFGC块接收延迟的输入时钟信号的多路复用器。属于同步组的第一输入时钟信号与属于同一同步组的第二输入时钟信号的切换等待时间是第二输入时钟信号的一个时钟周期。切换延迟是在电路的最终输出处没有出现时钟脉冲的周期。

2. 发明授权

US08086989B2 Structure for glitchless clock multiplexer optimized for synchronous and asynchronous clocks 有权
标题翻译：针对同步和异步时钟优化的无毛刺时钟复用器的结构
公开(公告)号：US08086989B2
公开(公告)日：2011-12-27
申请号：US12174572
申请日：2008-07-16
申请人： Eskinder Hailu , Takeo Yasuda
发明人： Eskinder Hailu , Takeo Yasuda
IPC分类号： G06F17/50
CPC分类号： G06F17/5059 , G06F2217/84
摘要： A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency (period in which no clock pulse appears at the final output of the circuit) from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal.
摘要翻译：用于使用针对同步和异步时钟优化的无毛刺时钟复用器的逻辑器件来切换时钟信号的电路的设计结构。该设计结构包括具有异步时钟组和一个或多个同步时钟组的电路。异步组包括用于异步时钟源的多个高频无毛刺控制（HFGC）块。每个同步组包括用于同步时钟源的多个HFGC块。该电路包括用于从用于异步时钟源的HFGC块和用于同步时钟源的HFGC块接收延迟的输入时钟信号的多路复用器。属于同步组的属于同步组的第一输入时钟信号与属于同一同步组的第二输入时钟信号的开关延迟（在电路的最终输出处没有出现时钟脉冲的周期）是第二输入时钟信号。

3. 发明申请

US20090164957A1 Design Structure for Glitchless Clock Multiplexer Optimized for Synchronous and Asynchronous Clocks 有权
标题翻译：用于同步和异步时钟优化的无毛刺时钟多路复用器的设计结构
公开(公告)号：US20090164957A1
公开(公告)日：2009-06-25
申请号：US12174572
申请日：2008-07-16
申请人： Eskinder Hailu , Takeo Yasuda
发明人： Eskinder Hailu , Takeo Yasuda
IPC分类号： G06F17/50
CPC分类号： G06F17/5059 , G06F2217/84
摘要： A design structure for a circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The design structure comprises a circuit having an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency (period in which no clock pulse appears at the final output of the circuit) from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal.
摘要翻译：用于使用针对同步和异步时钟优化的无毛刺时钟复用器的逻辑器件来切换时钟信号的电路的设计结构。该设计结构包括具有异步时钟组和一个或多个同步时钟组的电路。异步组包括用于异步时钟源的多个高频无毛刺控制（HFGC）块。每个同步组包括用于同步时钟源的多个HFGC块。该电路包括用于从用于异步时钟源的HFGC块和用于同步时钟源的HFGC块接收延迟的输入时钟信号的多路复用器。属于同步组的属于同步组的第一输入时钟信号与属于同一同步组的第二输入时钟信号的开关延迟（在电路的最终输出处没有出现时钟脉冲的周期）是第二输入时钟信号。

4. 发明申请

US20090160492A1 Glitchless Clock Multiplexer Optimized for Synchronous and ASynchronous Clocks 失效
标题翻译：无时钟多路复用器针对同步和异步时钟优化
公开(公告)号：US20090160492A1
公开(公告)日：2009-06-25
申请号：US11960832
申请日：2007-12-20
申请人： Eskinder Hailu , Takeo Yasuda
发明人： Eskinder Hailu , Takeo Yasuda
IPC分类号： H03K17/00
CPC分类号： H03K17/005 , G06F1/08
摘要： A circuit for switching clock signals with logic devices using a glitchless clock multiplexer optimized for synchronous and asynchronous clocks. The circuit comprises an asynchronous clock group and one or more synchronous clock group(s). The asynchronous group comprises a plurality of high frequency glitchless control (HFGC) blocks for asynchronous clock sources. Each synchronous group comprises a plurality of HFGC blocks for synchronous clock sources. The circuit comprises a multiplexer for receiving delayed input clock signals from HFGC blocks for asynchronous clock sources and from HFGC blocks for synchronous clock sources. A switching latency from a first input clock signal belonging to a synchronous group to a second input clock signal belonging to the same synchronous group is one clock cycle or less of the second input clock signal. Switching latency is the period in which no clock pulse appears at the final output of the circuit.
摘要翻译：用于使用针对同步和异步时钟优化的无毛刺时钟复用器的逻辑器件来切换时钟信号的电路。该电路包括异步时钟组和一个或多个同步时钟组。异步组包括用于异步时钟源的多个高频无毛刺控制（HFGC）块。每个同步组包括用于同步时钟源的多个HFGC块。该电路包括用于从用于异步时钟源的HFGC块和用于同步时钟源的HFGC块接收延迟的输入时钟信号的多路复用器。属于同步组的第一输入时钟信号与属于同一同步组的第二输入时钟信号的切换等待时间是第二输入时钟信号的一个时钟周期。切换延迟是在电路的最终输出处没有出现时钟脉冲的周期。

5. 发明授权

US08037431B2 Structure for interleaved voltage controlled oscillator 有权
标题翻译：交错压控振荡器的结构
公开(公告)号：US08037431B2
公开(公告)日：2011-10-11
申请号：US12126076
申请日：2008-05-23
申请人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
发明人： David W. Boerstler , Eskinder Hailu , Jieming Qi , Mike Shen
IPC分类号： G06F17/50 , H03K3/03
CPC分类号： H03L7/0995 , H03K3/0315 , H03K5/133
摘要： A design structure embodied in a machine readable medium used in a design process includes an interleaved voltage-controlled oscillator, including a ring circuit of main logic inverter gates; a plurality of delay elements connected in parallel with a selected sequence of the main logic inverter gates; wherein each delay element comprises a feedforward section, comprising controls for regulating signal transmission through feedforward elements responsive to one or more control voltages; and a proportional section for regulating signal transmission through at least one logic inverter gate; at least one temperature compensation circuit responsive to a compensating voltage input that is proportional to temperature; an electronic circuit in communication with the temperature compensation circuit and configured to provide a voltage signal responsive to temperature; an amplifier in connection with the electronic circuit to amplify the voltage signal; and a DC offset generator configured to adjust the voltage of the amplified voltage signal.
摘要翻译：体现在设计过程中使用的机器可读介质中的设计结构包括交错压控振荡器，包括主逻辑逆变器门的环形电路; 多个延迟元件，与所述主逻辑反相器门的选定序列并联连接; 其中每个延迟元件包括前馈部分，其包括用于响应于一个或多个控制电压来调节通过前馈元件的信号传输的控制; 以及用于调节通过至少一个逻辑反相器门的信号传输的比例部分; 响应于与温度成比例的补偿电压输入的至少一个温度补偿电路; 与所述温度补偿电路通信并且被配置为提供响应于温度的电压信号的电子电路; 与电子电路相连的放大器，用于放大电压信号; 以及配置成调整放大的电压信号的电压的DC偏移发生器。

6. 发明授权

US07747892B2 System for automatically selecting intermediate power supply voltages for intermediate level shifters 失效
标题翻译：用于自动选择中间电平转换器的中间电源电压的系统
公开(公告)号：US07747892B2
公开(公告)日：2010-06-29
申请号：US12036936
申请日：2008-02-25
申请人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Kazuhiko Miki , Jieming Qi
IPC分类号： G06F1/04
CPC分类号： H03K19/017581 , H03K19/00323 , H03K19/00346
摘要： The present invention provides for a system comprising a level shifter configured to receive a first clock signal from a first power domain, to receive a counter signal, to select one of a plurality of intermediate voltages in response to the received counter signal, and to generate a second clock signal in response to the received first clock signal and the selected intermediate voltage. A counter is coupled to the level shifter and configured to receive a divided clock signal and a comparison result signal, and to generate the counter signal in response to the received divided clock signal and comparison result signal. A divider is coupled to the counter and configured to receive the first clock signal and to generate the divided clock signal in response to the received first clock signal. A filter is coupled to the level shifter and configured to receive the second clock signal and to generate a first comparison signal in response to the received second clock signal. A fixed potential is configured to generate a second comparison signal. A comparator is coupled to the filter, the fixed potential, and the counter and configured to receive the first comparison signal and the second comparison signal, and to generate the comparison result signal in response to the received first comparison signal and the second comparison signal.
摘要翻译：本发明提供了一种系统，包括电平移位器，其被配置为从第一功率域接收第一时钟信号，以接收计数器信号，以响应于所接收的计数器信号选择多个中间电压中的一个，并产生响应于所接收的第一时钟信号和所选择的中间电压的第二时钟信号。计数器耦合到电平移位器并被配置为接收分频时钟信号和比较结果信号，并且响应于接收到的分频时钟信号和比较结果信号产生计数器信号。分频器耦合到计数器并且被配置为接收第一时钟信号并响应于接收到的第一时钟信号产生分频时钟信号。滤波器耦合到电平移位器并且被配置为接收第二时钟信号并响应于所接收的第二时钟信号产生第一比较信号。固定电位被配置为产生第二比较信号。比较器耦合到滤波器，固定电位和计数器，并且被配置为接收第一比较信号和第二比较信号，并且响应于接收的第一比较信号和第二比较信号产生比较结果信号。

7. 发明授权

US07716516B2 Method for controlling operation of microprocessor which performs duty cycle correction process 失效
标题翻译：用于控制执行占空比校正处理的微处理器的操作的方法
公开(公告)号：US07716516B2
公开(公告)日：2010-05-11
申请号：US11471819
申请日：2006-06-21
申请人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
发明人： Yosuke Muraki , Tetsuji Tamura , Iwao Takiguchi , Makoto Aikawa , Eskinder Hailu , Byron Lee Krauter , Stephen Douglas Weitzel , Jieming Qi , Kazuhiko Miki , David William Boerstler , Gilles Gervais , Kirk David Peterson , Robert Walter Berry, Jr. , Sang Hoo Dhong
IPC分类号： G06F1/04 , G06F1/24 , G06F11/00
CPC分类号： G06F1/04
摘要： A technology for supplying a power supply voltage to a microprocessor. Before normal arithmetic processing of the microprocessor, duty cycle correction process for adjusting the duty cycle of a clock signal inside the microprocessor is performed. In the duty cycle correction process for adjusting the duty cycle, the duty cycle of the clock signal is adjusted so as to minimize the power voltage at which the microprocessor is still operable.
摘要翻译：用于向微处理器提供电源电压的技术。在微处理器的正常运算处理之前，执行用于调整微处理器内的时钟信号占空比的占空比校正处理。在用于调整占空比的占空比校正处理中，调整时钟信号的占空比以使微处理器仍然可操作的电源电压最小化。

8. 发明授权

US07615788B2 Method for monolithically integrating silicon carbide microelectromechanical devices with electronic circuitry 有权
标题翻译：将碳化硅微机电器件与电子电路单片集成的方法
公开(公告)号：US07615788B2
公开(公告)日：2009-11-10
申请号：US11699713
申请日：2007-01-29
申请人： Kevin Kornegay , Andrew R. Atwell , Mihaela Balseanu , Jon Duster , Eskinder Hailu , Ce Li
发明人： Kevin Kornegay , Andrew R. Atwell , Mihaela Balseanu , Jon Duster , Eskinder Hailu , Ce Li
IPC分类号： H01L29/84
CPC分类号： B81C1/00246 , B81C2203/0735
摘要： A device and method of forming electronics and microelectromechanical on a silicon carbide substrate having a slow etch rate is performed by forming circuitry on the substrate. A protective layer is formed over the circuitry having a slower etch rate than the etch rate of the silicon carbide substrate. Microelectromechanical structures supported by the substrate are then formed. The circuitry comprises a field effect transistor in one embodiment, and the protective layer comprises a heavy metal layer.
摘要翻译：通过在衬底上形成电路来执行在具有缓蚀刻速率的碳化硅衬底上形成电子学和微机电的器件和方法。在具有比碳化硅衬底的蚀刻速率更慢的蚀刻速率的电路上形成保护层。然后形成由基板支撑的微机电结构。在一个实施例中，电路包括场效应晶体管，保护层包括重金属层。

9. 发明授权

US07595675B2 Duty cycle measurement method and apparatus that operates in a calibration mode and a test mode 有权
标题翻译：在校准模式和测试模式下工作的占空比测量方法和装置
公开(公告)号：US07595675B2
公开(公告)日：2009-09-29
申请号：US11381031
申请日：2006-05-01
申请人： David William Boerstler , Eskinder Hailu , Jieming Qi
发明人： David William Boerstler , Eskinder Hailu , Jieming Qi
IPC分类号： H03K5/04
CPC分类号： G01R31/31727
摘要： The disclosed methodology and apparatus measure the duty cycle of a reference clock signal that a clock circuit supplies to a duty cycle measurement (DCM) circuit. In one embodiment, the DCM circuit includes a capacitor driven by a charge pump. The reference clock signal drives the charge pump. The clock circuit varies the duty cycle of the reference clock signal among a number of known duty cycle values. The DCM circuit stores resultant capacitor voltage values corresponding to each of the known duty cycle values in a data store. The DCM circuit applies a test clock signal having an unknown duty cycle to the capacitor via the charge pump, thus charging the capacitor to a new voltage value that corresponds to the duty cycle of the test clock signal. Control software accesses the data store to determine the duty cycle to which the test clock signal corresponds.
摘要翻译：所公开的方法和装置测量时钟电路提供给占空比测量（DCM）电路的参考时钟信号的占空比。在一个实施例中，DCM电路包括由电荷泵驱动的电容器。参考时钟信号驱动电荷泵。时钟电路在多个已知的占空比值之间改变参考时钟信号的占空比。 DCM电路将对应于每个已知占空比值的合成电容电压值存储在数据存储器中。 DCM电路通过电荷泵向电容器施加具有未知占空比的测试时钟信号，从而将电容器充电到对应于测试时钟信号占空比的新电压值。控制软件访问数据存储，以确定测试时钟信号对应的占空比。

10. 发明申请

US20090132971A1 Structure for a Circuit Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler 失效
标题翻译：获得期望的锁相环占空比的电路的结构，不需要预定标器
公开(公告)号：US20090132971A1
公开(公告)日：2009-05-21
申请号：US12130040
申请日：2008-05-30
申请人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
发明人： David W. Boerstler , Eskinder Hailu , Masaaki Kaneko , Jieming Qi
IPC分类号： H03B19/00 , G06F17/50
CPC分类号： G06F17/5045 , H03K3/017 , H03L7/0995 , H03L2207/06
摘要： A design structure for a circuit for obtaining a desired phase locked loop (PLL) duty cycle without a pre-scaler is provided. The PLL circuit of the illustrative embodiments utilizes two separate loops that simultaneously operate on the VCO. One loop ensures the frequency and phase lock while the other loop ensures the duty cycle lock. The VCO is modified to have an additional control port to adjust the duty cycle. Thus, the VCO has one control port for performing frequency adjustment and one control port for duty cycle adjustment. As a result, both the duty cycle and the frequency may be controlled using the VCO of the PLL circuit of the illustrative embodiments so as to achieve any desired duty cycle output without requiring a VCO pre-scaler circuit or duty cycle correction circuit.
摘要翻译：提供了一种用于在没有预定标器的情况下获得期望的锁相环（PLL）占空比的电路的设计结构。说明性实施例的PLL电路利用在VCO上同时工作的两个单独的环路。一个环路确保频率和相位锁定，而另一个环路确保占空比锁定。 VCO被修改为具有附加的控制端口来调整占空比。因此，VCO具有用于执行频率调整的一个控制端口和用于占空比调整的一个控制端口。结果，可以使用说明性实施例的PLL电路的VCO来控制占空比和频率，以便实现任何期望的占空比输出，而不需要VCO预定标器电路或占空比校正电路。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式