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1. 发明授权

US06735180B1 Method of sending feedback information in a fast automatic repeat request forming part of an overall wireless communication system 有权
标题翻译：在构成整个无线通信系统的一部分的快速自动重复请求中发送反馈信息的方法
公开(公告)号：US06735180B1
公开(公告)日：2004-05-11
申请号：US09608643
申请日：2000-06-30
申请人： Esa Malkamäki , Deepak Mathew , Kari Pehkonen , Jussi Kähtävä
发明人： Esa Malkamäki , Deepak Mathew , Kari Pehkonen , Jussi Kähtävä
IPC分类号： H04B144
CPC分类号： H04L1/0068 , H04L1/0025 , H04L1/0028 , H04L1/0071 , H04L1/0073 , H04L1/1671 , H04L1/1812 , H04L1/1845
摘要： A method of sending feedback information in a fast physical layer hybrid automatic repeat request (HARQ) for frequency division duplex communications that form an overall wireless communication system is described in which the received packets are acknowledged by transmitting feedback data to the sender, wherein the acknowledgement comprises the reservation of obtaining a plurality of slots in the uplink/downlink dedicated channel radio frame for the feedback data alone. It is also directed to the transmission of feedback data used in specified slots within each radio frame, wherein the first slot used is based upon the time offset between uplink and downlink channels, as well as based upon the time required for de-interleaving, de-ratematching, decoding and error checking. In an alternative embodiment, the method uses dedicated physical control channel (DPCCH) bits in at least some of the slots for transmitting such feedback data to the sender.
摘要翻译：描述了在形成整体无线通信系统的用于频分双工通信的快速物理层混合自动重传请求（HARQ）中发送反馈信息的方法，其中通过向发送方发送反馈数据来确认所接收的分组，其中确认包括仅在反馈数据的上行链路/下行链路专用信道无线电帧中获得多个时隙的预留。它还针对在每个无线电帧内在指定时隙中使用的反馈数据的传输，其中所使用的第一时隙基于上行链路和下行链路信道之间的时间偏移，以及基于去交织所需的时间，de - 匹配，解码和错误检查。在替代实施例中，该方法使用至少一些时隙中的专用物理控制信道（DPCCH）比特来将这种反馈数据发送到发送方。

2. 再颁专利

USRE42744E1 Method of sending feedback information in a fast automatic repeat request forming part of an overall wireless communication system 有权
标题翻译：在构成整个无线通信系统的一部分的快速自动重复请求中发送反馈信息的方法
公开(公告)号：USRE42744E1
公开(公告)日：2011-09-27
申请号：US11267890
申请日：2005-11-04
申请人： Esa Malkamaki , Deepak Mathew , Kari Pehkonen , Jussi Kahtava
发明人： Esa Malkamaki , Deepak Mathew , Kari Pehkonen , Jussi Kahtava
IPC分类号： H04B1/44
CPC分类号： H04L1/0068 , H04L1/0025 , H04L1/0028 , H04L1/0071 , H04L1/0073 , H04L1/1671 , H04L1/1812 , H04L1/1845
摘要： A method of sending feedback information in a fast physical layer hybrid automatic repeat request (HARQ) for frequency division duplex communications that form an overall wireless communication system is described in which the received packets are acknowledged by transmitting feedback data to the sender, wherein the acknowledgement comprises the reservation of obtaining a plurality of slots in the uplink/downlink dedicated channel radio frame for the feedback data alone. It is also directed to the transmission of feedback data used in specified slots within each radio frame, wherein the first slot used is based upon the time offset between uplink and downlink channels, as well as based upon the time required for de-interleaving, de-ratematching, decoding and error checking. In an alternative embodiment, the method uses dedicated physical control channel (DPCCH) bits in at least some of the slots for transmitting such feedback data to the sender.
摘要翻译：描述了在形成整体无线通信系统的用于频分双工通信的快速物理层混合自动重传请求（HARQ）中发送反馈信息的方法，其中通过向发送方发送反馈数据来确认所接收的分组，其中确认包括仅在反馈数据的上行链路/下行链路专用信道无线电帧中获得多个时隙的预留。它还针对在每个无线电帧内在指定时隙中使用的反馈数据的传输，其中所使用的第一时隙基于上行链路和下行链路信道之间的时间偏移，以及基于去交织所需的时间，de - 匹配，解码和错误检查。在替代实施例中，该方法使用至少一些时隙中的专用物理控制信道（DPCCH）比特来将这种反馈数据发送到发送方。

3. 发明授权

US08316378B2 Data flow control in wireless communication systems 有权
标题翻译：无线通信系统中的数据流控制
公开(公告)号：US08316378B2
公开(公告)日：2012-11-20
申请号：US12254201
申请日：2008-10-20
申请人： John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
发明人： John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
IPC分类号： G06F9/44 , G06F15/16 , H04M1/64
CPC分类号： H04B1/71055 , H04B1/7105 , H04B2201/70711 , H04J13/0077
摘要： A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.
摘要翻译：一种方法包括在第一数据处理模块中接收数据，以及当接收到的数据的至少一个信号时隙包括符合第一数据传输标准的数据时启用第二数据处理模块。该方法还包括在第一数据处理模块和在处理器中执行的软件之间交换信号，以及确定第二数据处理模块的软件配置已经完成。该方法还包括处理第二数据处理模块中的至少一个信号时隙的数据，以及在完成对第二数据处理模块中的至少一个数据块的处理的完成时启用第三数据处理模块，并且确定第三数据处理模块的软件配置已经完成，所述至少一个数据块包括多个信号时隙。

4. 发明申请

US20080080542A1 Architecture for downlink receiver bit rate processor 审中-公开
标题翻译：下行接收器比特率处理器的架构
公开(公告)号：US20080080542A1
公开(公告)日：2008-04-03
申请号：US11529148
申请日：2006-09-28
申请人： Krishnan Vishwanathan , Deepak Mathew , Eric Aardoom , Lidwine Martinot , Aiguo Yan , Timothy Fisher-Jeffes , Paul D. Krivacek
发明人： Krishnan Vishwanathan , Deepak Mathew , Eric Aardoom , Lidwine Martinot , Aiguo Yan , Timothy Fisher-Jeffes , Paul D. Krivacek
IPC分类号： H04L12/56
CPC分类号： H04B1/707 , H04L1/005 , H04L1/0052 , H04L1/0054 , H04L1/0067
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

5. 发明申请

US20140059323A1 SYSTEMS AND METHODS OF DATA EXTRACTION IN A VECTOR PROCESSOR 有权
标题翻译：在矢量处理器中数据提取的系统和方法
公开(公告)号：US20140059323A1
公开(公告)日：2014-02-27
申请号：US13592617
申请日：2012-08-23
申请人： Jose Fridman , Ajay Anant Ingle , Deepak Mathew , Marc M. Hoffman , Michael John Lopez
发明人： Jose Fridman , Ajay Anant Ingle , Deepak Mathew , Marc M. Hoffman , Michael John Lopez
IPC分类号： G06F15/76
CPC分类号： G06F15/8084 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109
摘要： Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.
摘要翻译：公开了一种向量处理器中数据提取的系统和方法。在特定实施例中，向量处理器中的数据提取方法包括将至少一个数据元素复制到置换网络的源寄存器。该方法包括重新排序源寄存器的多个数据元素，用重新排序的数据元素填充置换网络的目的地寄存器，以及将重新排序的数据元素从目的地寄存器复制到存储器。

6. 发明授权

US08358988B2 Interface between chip rate processing and bit rate processing in wireless downlink receiver 有权
标题翻译：无线下行接收机芯片速率处理与比特率处理之间的接口
公开(公告)号：US08358988B2
公开(公告)日：2013-01-22
申请号：US11529146
申请日：2006-09-28
申请人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
发明人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/7105 , H04B2201/70707
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级并且提供编码的传输信道数据。后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。

7. 发明申请

US20080081575A1 Re-Quantization in downlink receiver bit rate processor 有权
标题翻译：下行接收器比特率处理器中的重量化
公开(公告)号：US20080081575A1
公开(公告)日：2008-04-03
申请号：US11529071
申请日：2006-09-28
申请人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
发明人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/707 , H04L1/0045 , H04L1/0071
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

8. 发明授权

US09342479B2 Systems and methods of data extraction in a vector processor 有权
标题翻译：矢量处理器中数据提取的系统和方法
公开(公告)号：US09342479B2
公开(公告)日：2016-05-17
申请号：US13592617
申请日：2012-08-23
申请人： Jose Fridman , Ajay Anant Ingle , Deepak Mathew , Marc M. Hoffman , Michael John Lopez
发明人： Jose Fridman , Ajay Anant Ingle , Deepak Mathew , Marc M. Hoffman , Michael John Lopez
IPC分类号： G06F9/00 , G06F15/80 , G06F9/30
CPC分类号： G06F15/8084 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30109
摘要： Systems and methods of data extraction in a vector processor are disclosed. In a particular embodiment a method of data extraction in a vector processor includes copying at least one data element to a source register of a permutation network. The method includes reordering multiple data elements of the source register, populating a destination register of the permutation network with the reordered data elements, and copying the reordered data elements from the destination register to a memory.
摘要翻译：公开了一种向量处理器中数据提取的系统和方法。在特定实施例中，向量处理器中的数据提取方法包括将至少一个数据元素复制到置换网络的源寄存器。该方法包括重新排序源寄存器的多个数据元素，用重新排序的数据元素填充置换网络的目的地寄存器，以及将重新排序的数据元素从目的地寄存器复制到存储器。

9. 发明授权

US08054922B2 Parameter estimation for modulated signals 有权
标题翻译：调制信号的参数估计
公开(公告)号：US08054922B2
公开(公告)日：2011-11-08
申请号：US12189529
申请日：2008-08-11
申请人： Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
发明人： Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
IPC分类号： H04B1/10
CPC分类号： H04L27/34 , H04L27/3809
摘要： A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.
摘要翻译：系统包括用于接收调制信号的接收机。接收机包括用于将表示调制信号的星座点的复数数据转换为标量数据表示的增益估计器。增益估计器被配置为将标量数据表示的第一部分折叠到标量数据表示的第二部分上。增益估计器还被配置为从标量数据表示的折叠的第一部分和第二部分估计星座增益值。

10. 发明申请

US20090165019A1 Data Flow Control 有权
标题翻译：数据流控制
公开(公告)号：US20090165019A1
公开(公告)日：2009-06-25
申请号：US12254201
申请日：2008-10-20
申请人： John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
发明人： John Zijun Shen , Carsten Aagaard Pedersen , Deepak Mathew , Paul Donald Krivacek , Aiguo Yan , Timothy Perrin Fisher-Jeffes
IPC分类号： G06F9/46
CPC分类号： H04B1/71055 , H04B1/7105 , H04B2201/70711 , H04J13/0077
摘要： A method includes receiving data in a first data processing module, and enabling a second data processing module when at least one signal time slot of the received data comprises data that complies with a first data transmission standard. The method also includes exchanging signals between the first data processing module and software executing in a processor, and determining that a software configuration of the second data processing module has been completed. The method also includes processing the data in the second data processing module for the at least one signal time slot, and enabling a third data processing module upon a completion of processing at least one data block in the second data processing module, and determining that a software configuration of the third data processing module has been completed, the at least one data block comprising multiple signal time slots.
摘要翻译：一种方法包括在第一数据处理模块中接收数据，以及当接收到的数据的至少一个信号时隙包括符合第一数据传输标准的数据时启用第二数据处理模块。该方法还包括在第一数据处理模块和在处理器中执行的软件之间交换信号，以及确定第二数据处理模块的软件配置已经完成。该方法还包括处理第二数据处理模块中的至少一个信号时隙的数据，以及在完成对第二数据处理模块中的至少一个数据块的处理的完成时启用第三数据处理模块，并且确定第三数据处理模块的软件配置已经完成，所述至少一个数据块包括多个信号时隙。

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