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1. 发明授权

US07266160B2 Method for joint DC offset correction and channel coefficient estimation in a receiver 有权
标题翻译：接收机中联合DC偏移校正和信道系数估计的方法
公开(公告)号：US07266160B2
公开(公告)日：2007-09-04
申请号：US10689330
申请日：2003-10-20
申请人： Marko Kocic , Lidwine Martinot , Zoran Zvonar
发明人： Marko Kocic , Lidwine Martinot , Zoran Zvonar
IPC分类号： H04L25/06
CPC分类号： H04L25/062 , H04L25/0216 , H04L25/023 , H04L25/025
摘要： Although DC offset reduction schemes can be applied in the analog domain, the residual static DCO in baseband is still present, significantly influencing the performance of high-level modulation schemes employed by recent high-data-rate wireless communications standards. In order to achieve satisfactory performance, DCO compensation algorithms are required in the digital domain. One such algorithm was developed which is based on joint estimation of the Channel Impulse Response (CIR) and the static DCO and ensures satisfactory performance of EDGE modem with direct conversion radio architectures. A further modification of the joint estimation algorithm, the so-called “perturbed joint L”, results in further improvement in the performance of the EDGE equalizer in critical fading channels.
摘要翻译：虽然DC偏移降低方案可以应用在模拟域中，但基带中的残留静态DCO仍然存在，从而显着影响近来高数据速率无线通信标准采用的高级调制方案的性能。为了达到令人满意的性能，数字领域需要DCO补偿算法。开发了一种这样的算法，其基于通道脉冲响应（CIR）和静态DCO的联合估计，并且确保具有直接转换无线电架构的EDGE调制解调器的令人满意的性能。联合估计算法（所谓的“扰动关节L”）的进一步修改导致EDGE均衡器在关键衰落信道中的性能的进一步改进。

2. 发明授权

US08548005B2 Technique for switching between 1x and 2x oversampling rate in a TD-SCDMA receiver 有权
标题翻译：在TD-SCDMA接收机中切换1x和2x过采样率的技术
公开(公告)号：US08548005B2
公开(公告)日：2013-10-01
申请号：US13090223
申请日：2011-04-19
申请人： Yonggang Hao , Aiguo Yan , Songsong Sun , Marko Kocic
发明人： Yonggang Hao , Aiguo Yan , Songsong Sun , Marko Kocic
IPC分类号： H04J13/00
CPC分类号： H04B1/7105
摘要： A TD-SCDMA receiver is provided that includes a joint detection (JD) block receiving a first input signal from a channel estimation block for signal detection. A short channel detection (SCD) block receives the first input signal and detecting the presence/absence of an AGWN-like channel based on the first input signal from the channel estimation block. The SCD block switches the JD block between 1× and 2× oversampling rates by sending to the JD block a second input signal.
摘要翻译：提供一种TD-SCDMA接收机，其包括从用于信号检测的信道估计块接收第一输入信号的联合检测（JD）块。短信道检测（SCD）块基于来自信道估计块的第一输入信号接收第一输入信号并检测AGWN样信道的存在/不存在。 SCD块通过向JD块发送第二个输入信号来将JD块切换到1×和2×过采样率之间。

3. 发明申请

US20130070833A1 ADVANCED JOINT DETECTION IN A TD-SCDMA SYSTEM 有权
标题翻译： TD-SCDMA系统中的高级联合检测
公开(公告)号：US20130070833A1
公开(公告)日：2013-03-21
申请号：US13235462
申请日：2011-09-18
申请人： Aiguo Yan , Yonggang Hao , Marko Kocic
发明人： Aiguo Yan , Yonggang Hao , Marko Kocic
IPC分类号： H04L27/06 , H03K5/00
CPC分类号： H04L25/0212 , H04L25/03038 , H04L25/03834
摘要： A communication system is provided that includes a composite transfer module that receives an input signal and performs one or more selective operations defined by a first transfer function on the input signal. The composite transfer module outputs a first signal. A joint detection module receives the first signal and performs joint detection on the first signal. The joint detection module utilizes channel estimation information of the first transfer function so as to allow the joint detection module to perform joint detection with an oversampling rate of 2× or higher.
摘要翻译：提供了一种通信系统，其包括复合传送模块，其接收输入信号并执行由输入信号上的第一传递函数定义的一个或多个选择性操作。复合传送模块输出第一信号。联合检测模块接收第一信号并对第一信号进行联合检测。联合检测模块利用第一传递函数的信道估计信息，以使联合检测模块以2×以上的过采样率进行联合检测。

4. 发明授权

US07953958B2 Architecture for joint detection hardware accelerator 有权
标题翻译：联合检测硬件加速器架构
公开(公告)号：US07953958B2
公开(公告)日：2011-05-31
申请号：US11818055
申请日：2007-06-12
申请人： John Zijun Shen , Paul D. Krivacek , Thomas J. Barber, Jr. , Lidwine Martinot , Aiguo Yan , Marko Kocic
发明人： John Zijun Shen , Paul D. Krivacek , Thomas J. Barber, Jr. , Lidwine Martinot , Aiguo Yan , Marko Kocic
IPC分类号： G06F15/76 , G06F9/302
CPC分类号： H04B1/7105 , H04B2201/70707 , H04B2201/70711
摘要： A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.
摘要翻译：联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测加速器和主机处理器。联合检测加速器可以包括用于存储输入数据值，中间结果和输出数据值的存储单元; 一个或多个计算单元，用于处理输入数据值和中间结果，并向存储器单元提供输出数据值; 控制器，用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。计算单元可以包括复数乘法单元，简化复乘法累积单元和归一化浮点除法器。存储器单元可以包括输入存储器，矩阵存储器，主存储器和输出存储器。

5. 发明申请

US20120269202A1 TECHNIQUE FOR SWITCHING BETWEEN 1X AND 2X OVERSAMPLING RATE IN A TD-SCDMA RECEIVER 有权
标题翻译：在TD-SCDMA接收机中切换1X和2X超频率的技术
公开(公告)号：US20120269202A1
公开(公告)日：2012-10-25
申请号：US13090223
申请日：2011-04-19
申请人： Yonggang Hao , Aiguo Yan , Songsong Sun , Marko Kocic
发明人： Yonggang Hao , Aiguo Yan , Songsong Sun , Marko Kocic
IPC分类号： H04J13/00
CPC分类号： H04B1/7105
摘要： A TD-SCDMA receiver is provided that includes a joint detection (JD) block receiving a first input signal from a channel estimation block for signal detection. A short channel detection (SCD) block receives the first input signal and detecting the presence/absence of an AGWN-like channel based on the first input signal from the channel estimation block. The SCD block switches the JD block between 1× and 2× oversampling rates by sending to the JD block a second input signal.
摘要翻译：提供一种TD-SCDMA接收机，其包括从用于信号检测的信道估计块接收第一输入信号的联合检测（JD）块。短信道检测（SCD）块基于来自信道估计块的第一输入信号接收第一输入信号并检测AGWN样信道的存在/不存在。 SCD块通过向JD块发送第二个输入信号来将JD块切换到1×和2×过采样率之间。

6. 发明授权

US08054922B2 Parameter estimation for modulated signals 有权
标题翻译：调制信号的参数估计
公开(公告)号：US08054922B2
公开(公告)日：2011-11-08
申请号：US12189529
申请日：2008-08-11
申请人： Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
发明人： Carsten Aagaard Pedersen , John Zijun Shen , Aiguo Yan , Deepak Mathew , Marko Kocic , Timothy Perrin Fisher-Jeffes , Thomas Keller
IPC分类号： H04B1/10
CPC分类号： H04L27/34 , H04L27/3809
摘要： A system includes a receiver for receiving a modulated signal. The receiver includes a gain estimator for converting complex data representative of constellation points of the modulated signal into scalar data representation. The gain estimator is configured to fold a first portion of the scalar data representation onto a second portion of the scalar data representation. The gain estimator is further configured to estimate a constellation gain value from the folded first portion and the second portion of the scalar data representation.
摘要翻译：系统包括用于接收调制信号的接收机。接收机包括用于将表示调制信号的星座点的复数数据转换为标量数据表示的增益估计器。增益估计器被配置为将标量数据表示的第一部分折叠到标量数据表示的第二部分上。增益估计器还被配置为从标量数据表示的折叠的第一部分和第二部分估计星座增益值。

7. 发明申请

US20080080468A1 Architecture for joint detection hardware accelerator 有权
标题翻译：联合检测硬件加速器架构
公开(公告)号：US20080080468A1
公开(公告)日：2008-04-03
申请号：US11818055
申请日：2007-06-12
申请人： John Zijun Shen , Paul D. Krivacek , Thomas J. Barber , Lidwine Martinot , Aiguo Yan , Marko Kocic
发明人： John Zijun Shen , Paul D. Krivacek , Thomas J. Barber , Lidwine Martinot , Aiguo Yan , Marko Kocic
IPC分类号： H04B7/216
CPC分类号： H04B1/7105 , H04B2201/70707 , H04B2201/70711
摘要： A joint detection system is configured to perform joint detection of received signals and includes ajoint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.
摘要翻译：联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测加速器和主机处理器。联合检测加速器可以包括用于存储输入数据值，中间结果和输出数据值的存储单元; 一个或多个计算单元，用于处理输入数据值和中间结果，并向存储器单元提供输出数据值; 控制器，用于控制存储器和一个或多个计算单元进行联合检测处理; 以及用于从主处理器接收输入数据值并向主机处理器提供输出数据值的外部接口。计算单元可以包括复数乘法单元，简化复乘法累积单元和归一化浮点除法器。存储器单元可以包括输入存储器，矩阵存储器，主存储器和输出存储器。

8. 发明授权

US08711986B2 Advanced joint detection in a TD-SCDMA system 有权
标题翻译： TD-SCDMA系统高级联合检测
公开(公告)号：US08711986B2
公开(公告)日：2014-04-29
申请号：US13235462
申请日：2011-09-18
申请人： Aiguo Yan , Yonggang Hao , Marko Kocic
发明人： Aiguo Yan , Yonggang Hao , Marko Kocic
IPC分类号： H04L27/06 , H04B1/10
CPC分类号： H04L25/0212 , H04L25/03038 , H04L25/03834
摘要： A communication system is provided that includes a composite transfer module that receives an input signal and performs one or more selective operations defined by a first transfer function on the input signal. The composite transfer module outputs a first signal. A joint detection module receives the first signal and performs joint detection on the first signal. The joint detection module utilizes channel estimation information of the first transfer function so as to allow the joint detection module to perform joint detection with an oversampling rate of 2× or higher.
摘要翻译：提供了一种通信系统，其包括复合传送模块，其接收输入信号并执行由输入信号上的第一传递函数定义的一个或多个选择性操作。复合传送模块输出第一信号。联合检测模块接收第一信号并对第一信号进行联合检测。联合检测模块利用第一传递函数的信道估计信息，以使联合检测模块以2×以上的过采样率进行联合检测。

9. 发明授权

US07916841B2 Method and apparatus for joint detection 有权
标题翻译：联合检测方法和装置
公开(公告)号：US07916841B2
公开(公告)日：2011-03-29
申请号：US11545857
申请日：2006-10-11
申请人： Aiguo Yan , Lidwine Martinot , Marko Kocic , Paul D. Krivacek , Thomas J. Barber, Jr. , John Zijun Shen
发明人： Aiguo Yan , Lidwine Martinot , Marko Kocic , Paul D. Krivacek , Thomas J. Barber, Jr. , John Zijun Shen
IPC分类号： H04M1/64 , H04L25/49
CPC分类号： H04B1/7105 , H04B2201/70711
摘要： A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.
摘要翻译：提供联合检测系统及相关方法。联合检测系统被配置为执行接收信号的联合检测，并且包括联合检测器加速器和可编程数字信号处理器（DSP）。联合检测器加速器被配置为执行输入到联合检测器加速器的第一数据的前端处理，并输出从前端处理得到的第二数据。联合检测器加速器还被配置为使用输入到联合检测器加速器的至少第三数据来执行后端处理。可编程DSP耦合到联合检测器加速器，并且可编程DSP被编程为使用由联合检测器加速器输出的第二数据执行至少一个中间处理操作。可编程DSP进一步编程为将由中间处理操作产生的第三数据输出到联合检测器加速器。

10. 发明申请

US20080089448A1 Fixed-point implementation of a joint detector 有权
标题翻译：联合检测器的定点实现
公开(公告)号：US20080089448A1
公开(公告)日：2008-04-17
申请号：US11546062
申请日：2006-10-11
申请人： Lidwine Martinot , Aiguo Yan , Marko Kocic , Thomas J. Barber , John Zijun Shen
发明人： Lidwine Martinot , Aiguo Yan , Marko Kocic , Thomas J. Barber , John Zijun Shen
IPC分类号： H04L27/06
CPC分类号： H04B1/7105 , H04B2201/70707 , H04L25/0224
摘要： A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.
摘要翻译：提供联合检测系统及相关方法。联合检测系统被配置为执行接收信号的联合检测。联合检测系统包括联合检测器加速器，其被配置为执行对接收信号的联合检测的操作，其中联合检测包括计算关节检测变量。该操作包括产生累加器中的值的乘法和累加运算，累加器中的值包括多个位。联合检测器加速器被配置为选择累加器中的值的多个比特的子集，其中选择的比特的子集是可配置的。联合检测器加速器还被配置为将位的子集存储到存储器中作为固定点表示。

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