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1. 发明申请

US20080080542A1 Architecture for downlink receiver bit rate processor 审中-公开
标题翻译：下行接收器比特率处理器的架构
公开(公告)号：US20080080542A1
公开(公告)日：2008-04-03
申请号：US11529148
申请日：2006-09-28
申请人： Krishnan Vishwanathan , Deepak Mathew , Eric Aardoom , Lidwine Martinot , Aiguo Yan , Timothy Fisher-Jeffes , Paul D. Krivacek
发明人： Krishnan Vishwanathan , Deepak Mathew , Eric Aardoom , Lidwine Martinot , Aiguo Yan , Timothy Fisher-Jeffes , Paul D. Krivacek
IPC分类号： H04L12/56
CPC分类号： H04B1/707 , H04L1/005 , H04L1/0052 , H04L1/0054 , H04L1/0067
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

2. 发明申请

US20080080443A1 Interface between chip rate processing and bit rate processing in wireless downlink receiver 有权
标题翻译：无线下行接收机芯片速率处理与比特率处理之间的接口
公开(公告)号：US20080080443A1
公开(公告)日：2008-04-03
申请号：US11529146
申请日：2006-09-28
申请人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
发明人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
IPC分类号： H04B7/216
CPC分类号： H04B1/7105 , H04B2201/70707
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

3. 发明授权

US08358988B2 Interface between chip rate processing and bit rate processing in wireless downlink receiver 有权
标题翻译：无线下行接收机芯片速率处理与比特率处理之间的接口
公开(公告)号：US08358988B2
公开(公告)日：2013-01-22
申请号：US11529146
申请日：2006-09-28
申请人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
发明人： Lidwine Martinot , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/7105 , H04B2201/70707
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级并且提供编码的传输信道数据。后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。

4. 发明授权

US08358987B2 Re-quantization in downlink receiver bit rate processor 有权
标题翻译：在下行链路接收机比特率处理器中重新量化
公开(公告)号：US08358987B2
公开(公告)日：2013-01-22
申请号：US11529071
申请日：2006-09-28
申请人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
发明人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/707 , H04L1/0045 , H04L1/0071
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data, an intermediate frame buffer that receives the de-mapped physical channel data, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data, a CRC checker and an output buffer.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，去映射物理信道数据的第一级，接收去映射物理信道数据的中间帧缓冲器，以及处理该去映射物理信道数据的第二级并且提供编码的传输信道数据。后端处理器可以包括第三级，包括缩放所编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据，CRC校验器和输出缓冲器。

5. 发明申请

US20080080444A1 Transport channel buffer organization in downlink receiver bit rate processor 审中-公开
标题翻译：下行接收器比特率处理器中的传输信道缓冲器组织
公开(公告)号：US20080080444A1
公开(公告)日：2008-04-03
申请号：US11529182
申请日：2006-09-28
申请人： Timothy Fisher-Jeffes , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan
发明人： Timothy Fisher-Jeffes , Deepak Mathew , Krishnan Vishwanathan , Eric Aardoom , Aiguo Yan
IPC分类号： H04B7/216
CPC分类号： H04L49/901 , H04L49/90
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

6. 发明申请

US20080081575A1 Re-Quantization in downlink receiver bit rate processor 有权
标题翻译：下行接收器比特率处理器中的重量化
公开(公告)号：US20080081575A1
公开(公告)日：2008-04-03
申请号：US11529071
申请日：2006-09-28
申请人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
发明人： Deepak Mathew , Aiguo Yan , Krishnan Vishwanathan , Eric Aardoom , Timothy Fisher-Jeffes
IPC分类号： H04B1/18
CPC分类号： H04B1/707 , H04L1/0045 , H04L1/0071
摘要： A bit rate processor in a wireless system includes a front end processor to process physical channel data and to generate encoded transport channel data, a transport channel buffer to hold the encoded transport channel data, and a back end processor to process the encoded transport channel data from the transport channel buffer and to generate decoded transport channel bits. The front end process may include a frame buffer that receives the physical channel data, a first stage to de-map the physical channel data from the frame buffer, an intermediate frame buffer that receives the de-mapped physical channel data from the first stage, and a second stage to process the de-mapped physical channel data and to provide the encoded transport channel data. The back end processor may include a third stage, including a scaling circuit to scale the encoded transport channel data, a decoder to decode the scaled transport channel data and a CRC checker to provide the decoded transport channel bits, and an output buffer to receive the decoded transport channel bits.
摘要翻译：无线系统中的比特率处理器包括用于处理物理信道数据并生成编码的传输信道数据的前端处理器，用于保存经编码的传输信道数据的传输信道缓冲器和用于处理编码的传输信道数据的后端处理器并且生成解码的传输信道位。前端处理可以包括接收物理信道数据的帧缓冲器，从帧缓冲器去映射物理信道数据的第一级，从第一级接收去映射物理信道数据的中间帧缓冲器，以及第二级，用于处理去映射的物理信道数据并提供经编码的传输信道数据。后端处理器可以包括第三级，包括缩放经编码的传输信道数据的缩放电路，解码器以解码缩放的传输信道数据和CRC校验器以提供解码的传输信道位，以及输出缓冲器，用于接收解码的传输信道位。

7. 发明授权

US08149702B2 Multi-mode bit rate processor 有权
标题翻译：多模比特率处理器
公开(公告)号：US08149702B2
公开(公告)日：2012-04-03
申请号：US12199640
申请日：2008-08-27
申请人： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
发明人： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
IPC分类号： H04J1/16
CPC分类号： G06F15/7842 , H04L1/0045 , H04L1/0052 , H04L1/1829
摘要： An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.
摘要翻译：一种用于在无线系统中处理信号的装置包括用于从一组物理信道接收输入数据的第一存储器模块，用于处理输入数据的第一多个子模块。第一多个子模块中的每一个被选择为基于数据和传输信道规范起作用。该装置还包括用于接收经处理的输入数据和输出中间数据的第二存储器模块。第二存储器中的输入数据的位置与数据和传输通道规范相关联地被分配。该装置还包括用于处理中间数据的第二多个子模块。第二多个子模块中的每一个被选择为基于数据和传输信道规范起作用。该装置还包括用于接收和输出比特率处理输出的第三存储器模块。

8. 发明申请

US20090175205A1 Multi-mode Bit Rate Processor 有权
标题翻译：多模式比特率处理器
公开(公告)号：US20090175205A1
公开(公告)日：2009-07-09
申请号：US12199640
申请日：2008-08-27
申请人： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
发明人： Deepak Mathew , Eric Aardoom , Timothy Perrin Fisher-Jeffes , David Stephen Ivory , Carsten Aagaard Pedersen , Aiguo Yan
IPC分类号： H04J1/00 , H04B7/216 , H04W88/02
CPC分类号： G06F15/7842 , H04L1/0045 , H04L1/0052 , H04L1/1829
摘要： An apparatus for processing signals in a wireless system includes a first memory module to receive input data from a set of physical channels, a first plurality of sub-modules to process the input data. Each of the first plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a second memory module to receive processed input data and output intermediate data. Locations of the input data in the second memory is allocated in connection with data and transmission channel specifications. The apparatus also includes a second plurality of sub-modules to process the intermediate data. Each of the second plurality of sub-modules is selected to function based upon data and transmission channel specifications. The apparatus also includes a third memory module to receive and output bit rate processing output.
摘要翻译：一种用于在无线系统中处理信号的装置包括用于从一组物理信道接收输入数据的第一存储器模块，用于处理输入数据的第一多个子模块。第一多个子模块中的每一个被选择为基于数据和传输信道规范起作用。该装置还包括用于接收经处理的输入数据和输出中间数据的第二存储器模块。第二存储器中的输入数据的位置与数据和传输通道规范相关联地被分配。该装置还包括用于处理中间数据的第二多个子模块。第二多个子模块中的每一个被选择为基于数据和传输信道规范起作用。该装置还包括用于接收和输出比特率处理输出的第三存储器模块。

9. 发明申请

US20050276316A1 Method and apparatus for receiving GPS/GLONASS signals 审中-公开
标题翻译：用于接收GPS / GLONASS信号的方法和装置
公开(公告)号：US20050276316A1
公开(公告)日：2005-12-15
申请号：US11139128
申请日：2005-05-26
申请人： Alain Rabaeijs , Eric Aardoom , Bert Gyselinckx , Marc Engels
发明人： Alain Rabaeijs , Eric Aardoom , Bert Gyselinckx , Marc Engels
IPC分类号： G01S1/00 , G01S19/22 , G01S19/30 , G01S19/32 , G01S19/33 , G01S19/37 , H04B1/707 , H04B15/00 , H04K1/00 , H04L27/30
CPC分类号： G01S19/32 , G01S19/22 , G01S19/30 , G01S19/33 , G01S19/37 , H04B1/707
摘要： An apparatus for processing received spread spectrum signals modulated with a unique pseudo-random code is disclosed. In one embodiment, the apparatus comprises i) a plurality of channel modules each including a correlator, ii) a circuit configured to hierarchically chain a plurality of the channel modules in series, wherein at least one of a code, control signals and carrier signals is passed from one channel module of the chain to the next, and iii) a selector configured to select the at least one of the code, control signals and carrier signals, to be transmitted to the next channel module in the chain with a delay or without a delay.
摘要翻译：公开了一种用于处理用唯一伪随机码调制的接收扩频信号的装置。在一个实施例中，该装置包括i）多个信道模块，每个信道模块包括相关器，ii）被配置为串联链接多个信道模块的电路，其中代码，控制信号和载波信号中的至少一个是从链路的一个通道模块传递到下一个通道模块，以及iii）选择器，其被配置为选择代码，控制信号和载波信号中的至少一个，以被延迟或没有传送到链中的下一个通道模块延迟。

10. 发明申请

US20060098721A1 Method and apparatus for receiving GPS/GLONASS signals 审中-公开
标题翻译：用于接收GPS / GLONASS信号的方法和装置
公开(公告)号：US20060098721A1
公开(公告)日：2006-05-11
申请号：US11302548
申请日：2005-12-13
申请人： Alain Rabaeijs , Eric Aardoom , Bert Gyselinckx , Marc Engels
发明人： Alain Rabaeijs , Eric Aardoom , Bert Gyselinckx , Marc Engels
IPC分类号： H04B1/707
CPC分类号： G01S19/32 , G01S19/22 , G01S19/30 , G01S19/33 , G01S19/37 , H04B1/707
摘要： A method of processing received L1 and L2 spread spectrum signals is disclosed. In one embodiment, the method comprises i) locally generating replicas of a known P-code, wherein each of the received signals includes a unique frequency carrier with the known pseudo-random P-code and an unknown code modulated thereon, ii) making the code replicas available at different relative phases, iii) demodulating the received L1 and L2 signals with replicas of the P-code, iv) repetitively and separately integrating the demodulated L1 and L2 signals over time periods related to the unknown code, and v) correlating an integration result for one of the L1 and L2 signals with an integration result for the other of the L1 and L2 signals.
摘要翻译：公开了一种处理接收的L1和L2扩展频谱信号的方法。在一个实施例中，该方法包括：i）本地生成已知P码的副本，其中每个接收信号包括具有已知伪随机P码和在其上调制的未知码的唯一频率载波，ii）代码复制品可用于不同的相对阶段，iii）用P代码的副本解调所接收的L1和L2信号，iv）在与未知代码相关的时间段上重复地和单独地对解调的L1和L2信号进行积分，以及v）相关 L1和L2信号之一的积分结果，具有L1和L2信号中另一个的积分结果。

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