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1. 发明授权

US07779320B2 Low power scan shifting with random-like test patterns 有权
标题翻译：低功耗扫描带有随机样的测试模式
公开(公告)号：US07779320B2
公开(公告)日：2010-08-17
申请号：US12070761
申请日：2008-02-21
申请人： Erik Chmelar
发明人： Erik Chmelar
IPC分类号： G01R31/28 , G06F11/00
CPC分类号： G01R31/318544 , G01R31/318385
摘要： An apparatus and method to design an integrated circuit (IC) to reduce the toggling during shifting in and shifting out of test patterns in a IC having scan chains, while maintaining random-like filling of the “don't cares” of a test set. An average pattern of test patterns of a test set is found for both cases of where the test set is fully specified and not fully specified, inverters are judiciously inserted into the scan path and each test pattern is then modified by XOR-ing it with the average test pattern to produce a modified test pattern, which produces less toggling, translating to less power consumption. Further, the random filling of don't cares, as opposed to 0-fill, 1-fill, or adjacent fill, increases defect detection through collateral coverage.
摘要翻译：一种用于设计集成电路（IC）的装置和方法，以减少在具有扫描链的IC中移位和移出测试图案期间的切换，同时保持随机样填充“不关心”测试集。对于测试集完全指定且未完全指定的两种情况，都会找到测试集的测试模式的平均模式，将逆变器明智地插入到扫描路径中，然后通过将测试模式与平均测试模式产生修改的测试图案，其产生较少的切换，转化为较少的功耗。此外，随机填充不关心，而不是0填充，1填充或相邻填充，增加了通过抵押覆盖的缺陷检测。

2. 发明申请

US20060075614A1 Shoelace protector 审中-公开
标题翻译：鞋带保护
公开(公告)号：US20060075614A1
公开(公告)日：2006-04-13
申请号：US10961586
申请日：2004-10-12
申请人： Erik Chmelar
发明人： Erik Chmelar
IPC分类号： A43C1/04
CPC分类号： A43B23/24 , A43B3/0078 , A43C1/04 , A43C11/24 , Y10T24/3768
摘要： A shoelace protector that serves to protect a shoelace at or near the eyelet. The shoelace protector generally comprises a tube with a shaft and a base. The shaft protects the shoelace from damage and the base prevents the tube from being pushed or pulled completely through the eyelet. In the preferred embodiment of the present invention the tube is detachably secured to the shoe by inserting said tube into the eyelet and lacing the shoelace therethrough. In another embodiment of the invention the tube is permanently secured to the eyelet or upper of the shoe.
摘要翻译：鞋带保护器，用于保护眼罩上或附近的鞋带。鞋带保护器通常包括具有轴和底座的管。轴保护鞋带免受损坏，底座可防止管子被完全推入或拉出孔眼。在本发明的优选实施例中，通过将所述管插入孔眼并将鞋带穿过其中而将管可拆卸地固定到鞋上。在本发明的另一个实施例中，管永久地固定到鞋眼或鞋的鞋面上。

3. 发明申请

US20100195776A1 Systems and Methods for Synchronous, Retimed Analog to Digital Conversion 失效
标题翻译：用于同步，重定时模数转换的系统和方法
公开(公告)号：US20100195776A1
公开(公告)日：2010-08-05
申请号：US12669482
申请日：2008-06-06
申请人： Erik Chmelar , Choshu Ito , William Loh
发明人： Erik Chmelar , Choshu Ito , William Loh
IPC分类号： H04L7/02 , H03K5/153
CPC分类号： H03M1/1215 , H03M1/002 , H03M1/361
摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a latch based analog to digital converter is disclosed that includes a first interleave with a set of comparators, a selector circuit and a latch. The set of comparators is operable to compare an analog input with respective reference voltages, and is synchronized to a clock phase. The selector circuit is operable to select an output of one of the set of comparators based at least in part on a selector input. A first interleave output is derived from the selected output. The latch receives a second interleave output from a second interleave and is transparent when the clock phase is asserted. The selector input includes an output of the latch.
摘要翻译：本发明的各种实施例提供了用于模数转换的系统和方法。例如，公开了一种基于锁存器的模数转换器，其包括与一组比较器的第一交错，选择器电路和锁存器。该组比较器可操作以将模拟输入与相应的参考电压进行比较，并且与时钟相位同步。选择器电路可操作以至少部分地基于选择器输入来选择该组比较器之一的输出。从所选择的输出中导出第一交错输出。锁存器接收来自第二交错的第二交织输出，并且在时钟相位被断言时是透明的。选择器输入包括锁存器的输出。

4. 发明授权

US07656339B2 Systems and methods for analog to digital conversion 有权
标题翻译：用于模数转换的系统和方法
公开(公告)号：US07656339B2
公开(公告)日：2010-02-02
申请号：US12134488
申请日：2008-06-06
申请人： Erik Chmelar
发明人： Erik Chmelar
IPC分类号： H03M1/36
CPC分类号： H03M1/182 , H03M1/002 , H03M1/004 , H03M1/361 , H03M1/367
摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, an analog to digital converter is disclosed that includes an analog input that is provided to a comparator bank. The comparator bank receives a reference indicator, and is operable to provide a current output based at least in part on a comparison of the analog input with a reference threshold corresponding to the reference indicator. The analog to digital converter further includes a range selection filter that is operable to receive the current output and to generate the reference indicator based at least in part on a prior output of the comparator bank.
摘要翻译：本发明的各种实施例提供了用于模数转换的系统和方法。例如，公开了一种模数转换器，其包括提供给比较器组的模拟输入。比较器组接收参考指示符，并且可操作以至少部分地基于模拟输入与对应于参考指示符的参考阈值的比较来提供电流输出。模数转换器还包括范围选择滤波器，其可操作以至少部分地基于比较器组的先前输出来接收当前输出并产生参考指示符。

5. 发明申请

US20090267821A1 Analog-to-Digital Converter 有权
标题翻译：模数转换器
公开(公告)号：US20090267821A1
公开(公告)日：2009-10-29
申请号：US12108791
申请日：2008-04-24
申请人： Erik Chmelar , Choshu Ito
发明人： Erik Chmelar , Choshu Ito
IPC分类号： H03M1/36
CPC分类号： H03M1/182 , H03M1/002 , H03M1/004 , H03M1/361 , H03M1/367
摘要： An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.
摘要翻译： ADC电路包括多个比较器和耦合到比较器的控制器。每个比较器可操作以产生指示表示施加到ADC电路的输入信号的第一信号与对应的参考信号之间的差的输出。控制器可操作以执行以下至少之一：（i）在给定的采样周期期间激活比较器的子集; 和（ii）根据输入信号的电平来控制比较器的相应参考信号的电平。给定采样周期内的多个有源比较器不小于输入信号被量化的区域数量的一个。

6. 发明申请

US20070074351A1 Multipurpose skateboard tool 失效
公开(公告)号：US20070074351A1
公开(公告)日：2007-04-05
申请号：US11242462
申请日：2005-10-04
申请人： Erik Chmelar
发明人： Erik Chmelar
IPC分类号： B25F1/00 , B25B15/00 , B25B23/16
CPC分类号： B25B13/48 , A63C17/0006 , B25F1/02 , B25H3/003
摘要： A compact multipurpose tool including a bit head, a hollow first cylinder that defines a plurality of open-end wrenches on one end, and a second cylinder that communicates with the bit head and can be at least partially housed within the hollow first cylinder. In further features the hollow first cylinder defines a socket on the end opposite the plurality of open-end wrenches and the second cylinder includes a plurality of sockets.

7. 发明申请

US20060156128A1 System and method for implementing postponed quasi-masking test output compression in integrated circuit 有权
标题翻译：在集成电路中实施延迟准掩蔽测试输出压缩的系统和方法
公开(公告)号：US20060156128A1
公开(公告)日：2006-07-13
申请号：US11013641
申请日：2004-12-16
申请人： Mikhail Grinchuk , Ahmad Alyamani , Erik Chmelar
发明人： Mikhail Grinchuk , Ahmad Alyamani , Erik Chmelar
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： The present invention provides a system and method for implementing postponed quasi-masking test output compression in an integrated circuit. The system includes a compressor for compressing a test response from N scan chains of an integrated circuit into M outputs. The test response may indicate faults in the integrated circuit. M and N are positive integers. The system further includes a correctable multiple input signature register with a size of M, which is communicatively coupled to the compressor. The correctable multiple input signature register is suitable for receiving the M outputs from the compressor as data inputs (s[0], . . . , s[M−1]) and receiving M correction bits (c[0], . . . , c[M−1]) and L address bits (a[0], . . . , a[L−1]) as correction inputs, L being a positive integer, 2L>=M. The correctable multiple input signature register is suitable for detecting faults when there is no or at least one unknown value (i.e., X-value) in the test response.
摘要翻译：本发明提供一种用于在集成电路中实现延迟准掩蔽测试输出压缩的系统和方法。该系统包括用于将集成电路的N个扫描链的测试响应压缩为M个输出的压缩器。测试响应可能指示集成电路中的故障。 M和N是正整数。该系统进一步包括具有M的可校正多输入签名寄存器，该寄存器通信地耦合到压缩器。可纠正的多输入签名寄存器适用于从压缩器接收作为数据输入（s [0]，...，s [M-1]）和接收M个校正位（c [0]，...）的M个输出。，c [M-1]）和L地址位（a [0]，...，a [L-1]）作为校正输入，L为正整数， M. 可校正的多输入签名寄存器适合于在测试响应中没有或至少一个未知值（即，X值）时检测故障。

8. 发明申请

US20100194616A1 Systems and Methods for Synchronous, Retimed Analog to Digital Conversion 有权
标题翻译：用于同步，重定时模数转换的系统和方法
公开(公告)号：US20100194616A1
公开(公告)日：2010-08-05
申请号：US12669481
申请日：2008-06-06
申请人： Erik Chmelar , Choshu Ito , William Loh
发明人： Erik Chmelar , Choshu Ito , William Loh
IPC分类号： H03M1/12
CPC分类号： H03M1/1215 , H03M1/002 , H03M1/361
摘要： Various embodiments of the present invention provide systems and methods for analog to digital conversion. For example, a retimed analog to digital converter is disclosed that includes a first set of sub-level interleaves and a second set of sub-level interleaves. The first set of sub-level interleaves includes a first sub-level interleave with a first set of comparators synchronized to a first clock phase, and a second sub-level interleave with a second set of comparators synchronized to a second clock phase. The second set of sub-level interleaves includes a third sub-level interleave with a third set of comparators synchronized to a third clock phase, and a fourth sub-level interleave with a fourth set of comparators synchronized to a fourth clock phase. A global interleave selects one of the first set of comparators based at least in part on an output from the second set of sub-level interleaves, and one of the third set of comparators based at least in part on an output from the first set of sub-level interleaves. In some instances of the aforementioned embodiments, an output of the first sub-level interleave and an output of the second sub-level interleave are synchronized to the third clock phase, and an output of the third sub-level interleave and an output of the fourth sub-level interleave are synchronized to the first clock phase.
摘要翻译：本发明的各种实施例提供了用于模数转换的系统和方法。例如，公开了一种重新定时的模数转换器，其包括第一组子电平交织和第二组子电平交织。第一组子电平交织包括与第一时钟相位同步的第一组比较器的第一子电平交织以及与第二时钟相位同步的第二组比较器的第二子电平交织。第二组子电平交织包括与第三组比较器同步到第三时钟相位的第三子电平交织以及与第四时钟相位同步的第四组比较器的第四子电平交织。至少部分地基于来自第二组子电平交织组的输出和第三组比较器中的一个，至少部分地基于第一组比较器的输出，选择第一组比较器中的一个，子级交错。在上述实施例的一些情况下，第一子电平交织的输出和第二子电平交织的输出被同步到第三时钟相位，并且第三子电平交织的输出和第四子电平交错同步到第一时钟相位。

9. 发明授权

US07696915B2 Analog-to-digital converter having reduced number of activated comparators 有权
标题翻译：具有减少的激活的比较器数量的模数转换器
公开(公告)号：US07696915B2
公开(公告)日：2010-04-13
申请号：US12108791
申请日：2008-04-24
申请人： Erik Chmelar , Choshu Ito
发明人： Erik Chmelar , Choshu Ito
IPC分类号： H03M1/36
CPC分类号： H03M1/182 , H03M1/002 , H03M1/004 , H03M1/361 , H03M1/367
摘要： An ADC circuit includes multiple comparators and a controller coupled to the comparators. Each of the comparators is operative to generate an output indicative of a difference between a first signal representative of an input signal applied to the ADC circuit and a corresponding reference signal. The controller is operative to perform at least one of: (i) activating a subset of the comparators during a given sample period being; and (ii) controlling levels of the corresponding reference signals of the comparators as a function of a level of the input signal. A number of active comparators during the given sample period is no greater than one less than a number of regions into which the input signal is quantized.
摘要翻译： ADC电路包括多个比较器和耦合到比较器的控制器。每个比较器可操作以产生指示表示施加到ADC电路的输入信号的第一信号与对应的参考信号之间的差的输出。控制器可操作以执行以下至少之一：（i）在给定的采样周期期间激活比较器的子集; 和（ii）根据输入信号的电平来控制比较器的相应参考信号的电平。给定采样周期内的多个有源比较器不小于输入信号被量化的区域数量的一个。

10. 发明授权

US07328386B2 Methods for using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits 失效
标题翻译：在基于扫描的集成电路测试中使用X容错测试响应压缩中校验和的方法
公开(公告)号：US07328386B2
公开(公告)日：2008-02-05
申请号：US11131990
申请日：2005-05-18
申请人： Mikhail I. Grinchuk , Ahmad A. Alyamani , Erik Chmelar
发明人： Mikhail I. Grinchuk , Ahmad A. Alyamani , Erik Chmelar
IPC分类号： G01R31/28
CPC分类号： G01R31/318547
摘要： The invention relates to a method for using checksums in X-tolerant test response compaction in scan-based testing of integrated circuits. Flip-flops of a chip are treated as points of a discrete geometrical structure described in terms of points and lines, with each point representing a MUXed flip-flop holding a value, each line representing a checksum, and each set of parallel lines representing scan chains. The checksums for the flip-flops are calculated along a direction.
摘要翻译：本发明涉及一种在集成电路的基于扫描的测试中的X容限测试响应压缩中使用校验和的方法。芯片的触发器被视为以点和线来描述的离散几何结构的点，每个点表示保持值的多路复用触发器，每行表示校验和，并且每组平行线表示扫描链条触发器的校验和沿着一个方向计算。

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