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1. 发明申请

US20110029980A1 LOW DEPTH PROGRAMMABLE PRIORITY ENCODERS 有权
标题翻译：低密度可编程优先编码器
公开(公告)号：US20110029980A1
公开(公告)日：2011-02-03
申请号：US12902376
申请日：2010-10-12
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G06F9/46
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

2. 发明申请

US20100293421A1 LOW DEPTH PROGRAMMABLE PRIORITY ENCODERS 有权
标题翻译：低密度可编程优先编码器
公开(公告)号：US20100293421A1
公开(公告)日：2010-11-18
申请号：US12465810
申请日：2009-05-14
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G01R31/28
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

3. 发明申请

US20050005255A1 Process for designing comparators and adders of small depth 失效
标题翻译：设计较小深度的比较器和加法器的过程
公开(公告)号：US20050005255A1
公开(公告)日：2005-01-06
申请号：US10602570
申请日：2003-06-24
申请人： Mikhail Grinchuk , Anatoli Bolotov
发明人： Mikhail Grinchuk , Anatoli Bolotov
IPC分类号： G06F7/02 , G06F7/506 , G06F17/50
CPC分类号： G06F17/5045 , G06F7/02 , G06F7/506
摘要： Logic circuits for logical operations, based on a function fN=x1 OR (x2 AND (x3 OR (x4 AND . . . xN . . . ))) or f′N=x1 AND (x2 OR (x3 AND (x4 OR . . . xN . . . ))), are designed by defining a top portion of the logic circuit based on a pre-selected pattern of 2-input $ and @ gates. The top portion has N inputs and approximately N/3 outputs. A smaller logic circuit is defined having approximately N/3 inputs coupled to the outputs of the top portion. In one embodiment, the circuit is designed for a circuit having N′ inputs, where N′ is 3n or 2*3n, and the N′-N most significant inputs are set to fixed values. The extra gates are removed resulting in a minimum depth circuit. In another embodiment, the depth is further reduced in some cases by designing a circuit for N-1 inputs and transforming the circuit to an N-input circuit. The $ and @ gates are converted to AND and/or OR gates, depending on the function.
摘要翻译：用于逻辑运算的逻辑电路基于函数fN = x1 OR（x2 AND（x3 OR（x4 AND ... xN ...））或f'N = x1 AND（x2 OR（x3 AND（x4 OR。通过基于2输入$和@门的预先选择的模式来定义逻辑电路的顶部来设计。顶部有N个输入和大约N / 3个输出。定义了较小的逻辑电路，其具有耦合到顶部部分的输出的大约N / 3个输入。在一个实施例中，电路被设计用于具有N'个输入的电路，其中N'是3n或2 * 3n，并且N'-N个最高有效输入被设置为固定值。额外的门被去除，导致最小的深度电路。在另一个实施例中，通过设计用于N-1输入的电路并将电路变换成N输入电路，在一些情况下深度进一步降低。根据功能，$和@门将转换为AND和/或OR门。

4. 发明授权

US07949909B2 Address controlling in the MBIST chain architecture 有权
标题翻译：地址控制在MBIST链架构
公开(公告)号：US07949909B2
公开(公告)日：2011-05-24
申请号：US12183562
申请日：2008-07-31
申请人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
发明人： Alexandre Andreev , Anatoli Bolotov , Mikhail Grinchuk
IPC分类号： G11C29/00 , G01R31/28
CPC分类号： G11C29/32 , G11C8/16 , G11C2029/3202
摘要： A memory collar includes a first circuit, a second circuit and a third circuit. The first circuit may be configured to generate a first control signal, a second control signal and a third control signal in response to one or more test commands. The second circuit may be configured to generate a fourth control signal in response to said third control signal and the fourth control signal. The third circuit may be configured to generate one or more address sequences. The one or more address sequences are presented to a memory during a test mode.
摘要翻译：存储器环包括第一电路，第二电路和第三电路。第一电路可以被配置为响应于一个或多个测试命令产生第一控制信号，第二控制信号和第三控制信号。第二电路可以被配置为响应于所述第三控制信号和第四控制信号而产生第四控制信号。第三电路可以被配置为生成一个或多个地址序列。在测试模式期间将一个或多个地址序列呈现给存储器。

5. 发明申请

US20100086127A1 EFFICIENT IMPLEMENTATION OF ARITHMETICAL SECURE HASH TECHNIQUES 有权
标题翻译：有效实施算术安全技术
公开(公告)号：US20100086127A1
公开(公告)日：2010-04-08
申请号：US12246812
申请日：2008-10-07
申请人： Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
发明人： Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic , Andrej A. Zolotykh , Alexei V. Galatenko
IPC分类号： H04L9/06
CPC分类号： H04L9/0643 , H04L2209/125
摘要： An apparatus including an initialization circuit and a hash computation circuit. The initialization circuit may be configured to present a number of initialization values. The hash computation circuit may be configured to generate hash values for the message in response to the padded message blocks and the initialization values. The hash computation circuit generally performs a diagonal cut technique that simultaneously uses values from a plurality of different cycle rounds in a single cycle round analog.
摘要翻译：一种包括初始化电路和散列计算电路的装置。初始化电路可以被配置为呈现多个初始化值。哈希计算电路可以被配置为响应于填充的消息块和初始化值来生成消息的散列值。哈希计算电路通常执行对角切割技术，其同时使用来自单周期循环模拟中的多个不同循环回合的值。

6. 发明申请

US20060236176A1 Segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits 有权
标题翻译：分段可寻址扫描架构和实现集成电路扫描测试的方法
公开(公告)号：US20060236176A1
公开(公告)日：2006-10-19
申请号：US11097936
申请日：2005-03-31
申请人： Ahmad Alyamani , Mikhail Grinchuk , Erik Chmelar
发明人： Ahmad Alyamani , Mikhail Grinchuk , Erik Chmelar
IPC分类号： G01R31/28
CPC分类号： G01R31/318544
摘要： The present invention provides a segmented addressable scan architecture and method for implementing scan-based testing of integrated circuits. A scan chain is divided into a plurality of segments. For a test pattern, compatible segments of the plurality of segments are grouped into compatibility classes. All compatible segments or a subset of them within one of the compatibility classes are simultaneously loaded through selective activation.
摘要翻译：本发明提供了一种用于实现集成电路的基于扫描的测试的分段可寻址扫描架构和方法。扫描链被分成多个段。对于测试模式，多个段的兼容段被分组为兼容性类别。通过选择性激活，同时加载所有兼容性段或其中一个兼容性类别的子集。

7. 发明授权

US6109201A Resynthesis method for significant delay reduction 失效
标题翻译：重新延迟降低的再合成方法
公开(公告)号：US6109201A
公开(公告)日：2000-08-29
申请号：US10395
申请日：1998-01-21
申请人： Dusan Petranovic , Ranko Scepanovic , Stanislav V. Aleshin , Mikhail Grinchuk , Sergei Gashov
发明人： Dusan Petranovic , Ranko Scepanovic , Stanislav V. Aleshin , Mikhail Grinchuk , Sergei Gashov
IPC分类号： G06F17/50
CPC分类号： G06F17/505
摘要： Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the cells. Designing of the IC's require meeting real-world constraints one of which is the performance of the IC, or the period of time required by the integrated circuit to produce the output signals from the time the input signals are available. Typically, the performance of an integrated circuit is determined by the slowest path of the signals, called the critical path. The critical path is usually only a small portion of the IC. The present invention discloses a method and apparatus for transforming the circuits comprising the critical path, thereby increasing the performance of the entire IC. The transformation is performed by segmenting, or blocking, the cells which make up the critical path. Then, each block is transformed, or replaced, with a resynthesized circuit to which both the digital 0 and digital 1 values are provided. The critical path is defined by the fact that the delay at each block is accumulated because each block has to wait for the output signal of the preceding block to use as its input signal. After the resynthesis of the blocks, none of the blocks need to wait for the output signal of its preceding block because each of the resynthesized blocks has the output for all possible inputs values (0 and 1). Thus, the signal delay at each block is not accumulated; rather, the only accumulated delay is the delay of the multiplexors used to select the correct output. The result is a dramatically reduced critical path delay.
摘要翻译：集成电路芯片（IC）需要适当放置多个单元（电路组件组）和复杂的导线布线来连接单元。 IC的设计需要满足实际的限制，其中之一是IC的性能，或集成电路从输入信号可用时产生输出信号所需的时间段。通常，集成电路的性能由称为关键路径的信号的最慢路径决定。关键路径通常只是IC的一小部分。本发明公开了一种用于变换包括关键路径的电路的方法和装置，从而提高了整个IC的性能。通过分割或阻塞构成关键路径的单元来执行转换。然后，用提供数字0和数字1值的再合成电路对每个块进行变换或替换。关键路径由每个块的延迟积累的事实定义，因为每个块必须等待前一块的输出信号用作其输入信号。在块的再合成之后，没有一个块需要等待其前一块的输出信号，因为每个再合并块具有用于所有可能的输入值（0和1）的输出。因此，每个块的信号延迟不被累加; 相反，唯一累积的延迟是用于选择正确输出的多路复用器的延迟。结果是大大减少了关键路径延迟。

8. 发明授权

US08411853B2 Alternate galois field advanced encryption standard round 有权
标题翻译：替代galois域高级加密标准轮
公开(公告)号：US08411853B2
公开(公告)日：2013-04-02
申请号：US12200037
申请日：2008-08-28
申请人： Paul G. Filseth , Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic
发明人： Paul G. Filseth , Mikhail Grinchuk , Anatoli Bolotov , Lav D. Ivanovic
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , H04L2209/125
摘要： An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to (i) generate second Galois Field elements by performing a first Galois Field inversion on first Galois Field elements, the first Galois Field inversion being different from a second Galois Field inversion defined by an Advanced Encryption Standard and (ii) generate third Galois Field elements by multiplying the second Galois Field elements by an inverse of a predetermined matrix. The second circuit may be configured to (i) generate fourth Galois Field elements by processing the third Galois Field elements in a current encryption round while in a non-skip mode, (ii) generate fifth Galois Field elements by multiplying the fourth Galois Field elements by the predetermined matrix and (iii) present the fifth Galois Field elements as updated versions of the first Galois Field elements in advance of a next encryption round.
摘要翻译：公开了一种具有第一电路和第二电路的装置。第一电路可以被配置为（i）通过在第一伽罗瓦域元件上执行第一伽罗瓦域反演来产生第二伽罗瓦域元件，第一伽罗瓦域反转与由高级加密标准定义的第二伽罗瓦域反演不同，）通过将第二伽罗瓦域元素乘以预定矩阵的倒数来产生第三伽罗瓦域元素。第二电路可以被配置为（i）通过在非跳过模式下处理当前加密循环中的第三伽罗瓦域元素来产生第四伽罗瓦域元素，（ii）通过将第四伽罗瓦域元素乘以第四伽罗瓦域元素通过预定矩阵和（iii）在下一个加密轮次之前将第五伽罗瓦域元素呈现为第一伽罗瓦域元素的更新版本。

9. 发明授权

US08063659B2 Low depth programmable priority encoders 有权
标题翻译：低深度可编程优先编码器
公开(公告)号：US08063659B2
公开(公告)日：2011-11-22
申请号：US12902376
申请日：2010-10-12
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

10. 发明授权

US07839164B1 Low depth programmable priority encoders 有权
标题翻译：低深度可编程优先编码器
公开(公告)号：US07839164B1
公开(公告)日：2010-11-23
申请号：US12465810
申请日：2009-05-14
申请人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
发明人： Mikhail Grinchuk , Anatoli Bolotov , Sergei B. Gashkov , Lav D. Ivanovic
IPC分类号： G06F7/38 , H03K19/173
CPC分类号： G06F7/74
摘要： An apparatus having a plurality of first circuits, second circuits, third circuits and fourth circuits is disclosed. The first circuits may be configured to generate a plurality of first signals in response to (i) a priority signal and (ii) a request signal. The second circuits may be configured to generate a plurality of second signals in response to the first signals. The third circuits may be configured to generate a plurality of enable signals in response to the second signals. The fourth circuits may be configured to generate collectively an output signal in response to (i) the enable signals and (ii) the request signal. A combination of the first circuits, the second circuits, the third circuits and the fourth circuits generally establishes a programmable priority encoder. The second signals may be generated independent of the enable signals.
摘要翻译：公开了具有多个第一电路，第二电路，第三电路和第四电路的装置。第一电路可以被配置为响应于（i）优先级信号和（ii）请求信号而产生多个第一信号。第二电路可以被配置为响应于第一信号而产生多个第二信号。第三电路可以被配置为响应于第二信号而产生多个使能信号。第四电路可以被配置为响应于（i）使能信号和（ii）请求信号而一起产生输出信号。第一电路，第二电路，第三电路和第四电路的组合通常建立可编程优先编码器。可以独立于使能信号产生第二信号。

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