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1. 发明授权

US09075623B2 External auxiliary execution unit interface for format conversion of instruction from issue unit to off-chip auxiliary execution unit 有权
标题翻译：外部辅助执行单元接口，用于从发布单元到片外辅助执行单元的指令格式转换
公开(公告)号：US09075623B2
公开(公告)日：2015-07-07
申请号：US13352907
申请日：2012-01-18
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Corey V. Swenson
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Corey V. Swenson
IPC分类号： G06F9/38 , G06F15/80 , G06F15/78
CPC分类号： G06F9/3881 , G06F9/3877 , G06F15/7864 , G06F15/8038
摘要： An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to integrate the AXU with an issue unit, a fixed point execution unit, and optionally other functional units in the processing core. The external AXU interface enables the issue unit to issue instructions to the AXU in much the same manner as the issue unit would be able to issue instructions to an AXU that was disposed on the same chip. By doing so, the AXU on the second programmable chip can be designed, tested and verified independent of the processing core on the first programmable chip, thereby enabling a common processing core, which has been designed, tested, and verified, to be used in connection with multiple different AXU designs.
摘要翻译：在设置在第一可编程芯片中的处理核心和设置在第二可编程芯片中的芯片外AXU之间提供外部辅助执行单元（AXU）接口，以将AXU与发行单元，固定点执行单元以及可选地处理核心中的其他功能单元。外部AXU接口使发布单元能够以与发布单元能够向安置在同一芯片上的AXU发出指令的方式大致相同的方式向AXU发出指令。通过这样做，可以独立于第一可编程芯片上的处理核心设计，测试和验证第二可编程芯片上的AXU，从而使已经设计，测试和验证的公共处理核心被用于连接多个不同的AXU设计。

2. 发明申请

US20130185542A1 EXTERNAL AUXILIARY EXECUTION UNIT INTERFACE TO OFF-CHIP AUXILIARY EXECUTION UNIT 有权
标题翻译：外部辅助执行单元接口切换辅助执行单元
公开(公告)号：US20130185542A1
公开(公告)日：2013-07-18
申请号：US13352907
申请日：2012-01-18
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Corey V. Swenson
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Corey V. Swenson
IPC分类号： G06F9/30
CPC分类号： G06F9/3881 , G06F9/3877 , G06F15/7864 , G06F15/8038
摘要： An external Auxiliary Execution Unit (AXU) interface is provided between a processing core disposed in a first programmable chip and an off-chip AXU disposed in a second programmable chip to integrate the AXU with an issue unit, a fixed point execution unit, and optionally other functional units in the processing core. The external AXU interface enables the issue unit to issue instructions to the AXU in much the same manner as the issue unit would be able to issue instructions to an AXU that was disposed on the same chip. By doing so, the AXU on the second programmable chip can be designed, tested and verified independent of the processing core on the first programmable chip, thereby enabling a common processing core, which has been designed, tested, and verified, to be used in connection with multiple different AXU designs.
摘要翻译：在设置在第一可编程芯片中的处理核心和设置在第二可编程芯片中的芯片外AXU之间提供外部辅助执行单元（AXU）接口，以将AXU与发行单元，固定点执行单元以及可选地处理核心中的其他功能单元。外部AXU接口使发布单元能够以与发布单元能够向安置在同一芯片上的AXU发出指令的方式大致相同的方式向AXU发出指令。通过这样做，可以独立于第一可编程芯片上的处理核心设计，测试和验证第二可编程芯片上的AXU，从而使已经设计，测试和验证的公共处理核心被用于连接多个不同的AXU设计。

3. 发明授权

US08494833B2 Emulating a computer run time environment 有权
标题翻译：模拟电脑运行时环境
公开(公告)号：US08494833B2
公开(公告)日：2013-07-23
申请号：US12118059
申请日：2008-05-09
申请人： Eric O. Mejdrich , Paul E. Schardt , Corey V. Swenson
发明人： Eric O. Mejdrich , Paul E. Schardt , Corey V. Swenson
IPC分类号： G06F9/455 , G06F9/45
CPC分类号： G06F9/45533
摘要： Emulating a computer run time environment including: storing translated code in blocks of a translated code cache, each block of the translated code cache designated for storage of translated code for a separate one of the target executable processes, including identifying each block in dependence upon an identifier of the process for which the block is designated as storage; executing by the emulation environment a particular one of the target executable processes, using for target code translation the translated code in the block of the translated code cache designated as storage for the particular process; and upon encountering a context switch by the target operating system to execution of a new target executable process, changing from the block designated for the particular process to using for target code translation the translated code in the block of the translated code cache designated as storage for the new target executable process.
摘要翻译：模拟计算机运行时间环境，包括：将转换后的代码存储在翻译的代码高速缓存的块中，转换的代码缓存的每个块被指定用于存储针对目标可执行进程的单独的一个的转换的代码，包括依赖于将块指定为存储的进程的标识符; 由仿真环境执行目标可执行过程中的特定一个，使用目标代码将被转换的代码缓存的块中的转换后的代码转换为特定进程的存储; 并且当遇到由目标操作系统执行新的目标可执行过程的上下文切换时，从为特定进程指定的块改变为使用目标代码转换所转换的代码缓存的块中被转换的代码缓存指定为存储新的目标可执行过程。

4. 发明申请

US20090282139A1 Emulating A Computer Run Time Environment 有权
标题翻译：仿真计算机运行时环境
公开(公告)号：US20090282139A1
公开(公告)日：2009-11-12
申请号：US12118059
申请日：2008-05-09
申请人： Eric O. Mejdrich , Paul E. Schardt , Corey V. Swenson
发明人： Eric O. Mejdrich , Paul E. Schardt , Corey V. Swenson
IPC分类号： G06F9/455 , G06F15/16
CPC分类号： G06F9/45533
摘要： Emulating a computer run time environment including: storing translated code in blocks of a translated code cache, each block of the translated code cache designated for storage of translated code for a separate one of the target executable processes, including identifying each block in dependence upon an identifier of the process for which the block is designated as storage; executing by the emulation environment a particular one of the target executable processes, using for target code translation the translated code in the block of the translated code cache designated as storage for the particular process; and upon encountering a context switch by the target operating system to execution of a new target executable process, changing from the block designated for the particular process to using for target code translation the translated code in the block of the translated code cache designated as storage for the new target executable process.
摘要翻译：模拟计算机运行时间环境，包括：将转换后的代码存储在翻译的代码高速缓存的块中，转换的代码缓存的每个块被指定用于存储针对目标可执行进程的单独的一个的转换的代码，包括依赖于将块指定为存储的进程的标识符; 由仿真环境执行目标可执行过程中的特定一个，使用目标代码将被转换的代码缓存的块中的转换后的代码转换为特定进程的存储; 并且当遇到由目标操作系统执行新的目标可执行过程的上下文切换时，从为特定进程指定的块改变为使用目标代码转换所转换的代码缓存的块中被转换的代码缓存指定为存储新的目标可执行过程。

5. 发明申请

US20090271172A1 Emulating A Computer Run Time Environment 审中-公开
标题翻译：仿真计算机运行时环境
公开(公告)号：US20090271172A1
公开(公告)日：2009-10-29
申请号：US12108770
申请日：2008-04-24
申请人： Eric O. Mejdrich , Paul E. Schardt , Corey V. Swenson
发明人： Eric O. Mejdrich , Paul E. Schardt , Corey V. Swenson
IPC分类号： G06F9/455
CPC分类号： G06F9/45554
摘要： Emulating a computer run time environment as a component of a dynamic binary translation loop that translates target executable code compiled for execution on a target computer to code executable on a host computer of a kind other than the target computer, the target executable code including function calls to functions to be translated. Embodiments of the present invention include: determining, upon encountering in the binary translation loop a function call to a function to be translated, that the function call is a call to a host library function in a host native library; hashing a target executable image of the function to be translated from the target executable code, thereby producing a hash value; and using the hash value as an index to retrieve from a thunk table a host native address of the host library function in the host native library.
摘要翻译：将计算机运行时环境作为动态二进制翻译循环的组成部分，将目标计算机上编译的目标可执行代码转换为在目标计算机之外的主机上的可执行代码，目标可执行代码包括函数调用要翻译的功能。本发明的实施例包括：当在二进制翻译循环中遇到对待转换的函数的函数调用时，确定函数调用是对主机本地库中的主机库函数的调用; 从目标可执行代码散列要转换的功能的目标可执行映像，从而产生散列值; 并使用哈希值作为索引从主表中检索宿主本机库中主机库函数的主机本机地址。

6. 发明授权

US08898396B2 Software pipelining on a network on chip 有权
标题翻译：软件流水线在片上网络上
公开(公告)号：US08898396B2
公开(公告)日：2014-11-25
申请号：US13453380
申请日：2012-04-23
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28 , H04L12/879 , H04L12/933 , H04L12/861 , H04L12/935 , H04L12/947
CPC分类号： H04L49/15 , H04L49/109 , H04L49/252 , H04L49/3036 , H04L49/90 , H04L49/901
摘要： Memory sharing in a software pipeline on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution; allocating memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and deallocating the shared memory.
摘要翻译：在芯片上的软件管道（“NOC”）中的内存共享，NOC包括集成处理器（IP）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器通信控制器和网络接口控制器，其中每个存储器通信控制器控制IP块和存储器之间的通信以及控制通过路由器进行IP间块通信的每个网络接口控制器，包括将计算机软件应用程序分段成软件流水线的阶段，所述软件流水线包括一个或多个执行路径; 在至少两个阶段中分配要共享的存储器，包括创建智能指针，所述智能指针包括用于确定何时可以释放所述共享存储器的数据元素; 根据用于确定何时可以释放共享存储器的数据元素确定可以释放共享存储器; 并释放共享内存。

7. 发明授权

US08719455B2 DMA-based acceleration of command push buffer between host and target devices 失效
标题翻译：主机和目标设备之间基于DMA的加速命令推送缓冲区
公开(公告)号：US08719455B2
公开(公告)日：2014-05-06
申请号：US12824674
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F3/00 , G06F13/28
CPC分类号： G06F13/28
摘要： Direct Memory Access (DMA) is used in connection with passing commands between a host device and a target device coupled via a push buffer. Commands passed to a push buffer by a host device may be accumulated by the host device prior to forwarding the commands to the push buffer, such that DMA may be used to collectively pass a block of commands to the push buffer. In addition, a host device may utilize DMA to pass command parameters for commands to a command buffer that is accessible by the target device but is separate from the push buffer, with the commands that are passed to the push buffer including pointers to the associated command parameters in the command buffer.
摘要翻译：直接存储器访问（DMA）用于在通过推送缓冲器耦合的主机设备和目标设备之间传递命令。由宿主设备传递到推送缓冲器的命令可以在将命令转发到推送缓冲器之前被主机设备累积，使得可以使用DMA来共同地将一组命令传递给推送缓冲器。此外，主机设备可以利用DMA将用于命令的命令参数传递给目标设备可访问但与推送缓冲区分离的命令缓冲区，其中传递到推送缓冲器的命令包括指向相关命令的指针命令缓冲区中的参数。

8. 发明授权

US08692825B2 Parallelized streaming accelerated data structure generation 失效
标题翻译：并行流加速数据结构生成
公开(公告)号：US08692825B2
公开(公告)日：2014-04-08
申请号：US12822427
申请日：2010-06-24
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G09G5/00
CPC分类号： G06T15/06 , G06T2200/28 , G06T2210/52
摘要： A method includes receiving at a master processing element primitive data that includes properties of a primitive. The method includes partially traversing a spatial data structure that represents a three-dimensional image to identify an internal node of the spatial data structure. The internal node represents a portion of the three-dimensional image. The method also includes selecting a slave processing element from a plurality of slave processing elements. The selected processing element is associated with the internal node. The method further includes sending the primitive data to the selected slave processing element to traverse a portion of the spatial data structure to identify a leaf node of the spatial data structure.
摘要翻译：一种方法包括在主处理元件处接收包括原语的属性的原始数据。该方法包括部分地遍历表示三维图像以识别空间数据结构的内部节点的空间数据结构。内部节点表示三维图像的一部分。该方法还包括从多个从属处理元件中选择从属处理元件。所选择的处理元件与内部节点相关联。该方法还包括将原始数据发送到所选择的从属处理元件以遍历空间数据结构的一部分以识别空间数据结构的叶节点。

9. 发明授权

US08514232B2 Propagating shared state changes to multiple threads within a multithreaded processing environment 有权
标题翻译：将共享状态更改传播到多线程处理环境中的多个线程
公开(公告)号：US08514232B2
公开(公告)日：2013-08-20
申请号：US12824778
申请日：2010-06-28
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer , Matthew R. Tubbs
IPC分类号： G06F15/80
CPC分类号： G06F12/0813 , G06T15/005
摘要： A circuit arrangement and method make state changes to shared state data in a highly multithreaded environment by propagating or streaming the changes to multiple parallel hardware threads of execution in the multithreaded environment using an on-chip communications network and without attempting to access any copy of the shared state data in a shared memory to which the parallel threads of execution are also coupled.
摘要翻译：电路布置和方法通过使用片上通信网络在多线程环境中传播或将变化传播或传输到多个并行硬件执行线程而不尝试访问任何副本，从而使状态对高度多线程环境中的共享状态数据进行改变并行线程执行的共享存储器中的共享状态数据也被耦合。

10. 发明授权

US08473667B2 Network on chip that maintains cache coherency with invalidation messages 有权
标题翻译：使用无效信息维护高速缓存一致性的片上网络
公开(公告)号：US08473667B2
公开(公告)日：2013-06-25
申请号：US11972753
申请日：2008-01-11
申请人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
发明人： Eric O. Mejdrich , Paul E. Schardt , Robert A. Shearer
IPC分类号： G06F13/00
CPC分类号： G06F13/4027 , G06F12/0808 , G06F12/0815
摘要： A network on chip (‘NOC’), and methods of operation of a NOC, that maintains cache coherency with invalidation messages, the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC also including an invalidating module configured to send, to selected IP blocks, an invalidation message, the invalidation message representing an instruction to invalidate cached memory and the selected IP blocks, each selected IP block configured to invalidate the contents of the cached memory responsive to receiving the invalidation message.
摘要翻译：一个片上网络（NOC），以及NOC的操作方法，通过无效消息来保持高速缓存一致性，NOC包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器 IP块通过存储器通信控制器和网络接口控制器适配于路由器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器，NOC还包括无效模块，其被配置为向所选择的IP块发送无效消息，所述无效消息表示使缓存的存储器和所选择的IP块无效的指令，每个所选择的IP块被配置为响应于接收到所述无效消息而使所缓存的存储器的内容无效。

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