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1. 发明申请

US20110119551A1 Memory System with Error Detection and Retry Modes of Operation 有权
标题翻译：具有错误检测和重试操作模式的内存系统
公开(公告)号：US20110119551A1
公开(公告)日：2011-05-19
申请号：US12940942
申请日：2010-11-05
申请人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
发明人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC分类号： H04L1/18 , H03M13/15 , G06F11/10 , G06F11/14
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
摘要翻译：存储器系统包括具有至少一个信号线的链路和控制器。所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。至少一个接收器耦合到链路以接收第二数据。第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

2. 发明授权

US09141479B2 Memory system with error detection and retry modes of operation 有权
标题翻译：具有错误检测和重试操作模式的内存系统
公开(公告)号：US09141479B2
公开(公告)日：2015-09-22
申请号：US12940942
申请日：2010-11-05
申请人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
发明人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC分类号： H03M13/00 , G06F11/14 , G06F11/07 , G06F11/10 , H04L1/00 , H04L1/08 , H04L1/18 , G06F11/00
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
摘要翻译：存储器系统包括具有至少一个信号线的链路和控制器。所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。至少一个接收器耦合到链路以接收第二数据。第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

3. 发明授权

US06356975B1 Apparatus and method for pipelined memory operations 失效
公开(公告)号：US06356975B1
公开(公告)日：2002-03-12
申请号：US09169526
申请日：1998-10-09
申请人： Richard M. Barth , Ely K. Tsern , Mark A. Horowitz , Donald C. Stark , Craig E. Hampel , Frederick A. Ware , John B. Dillon , by Nancy David Dillon
发明人： Richard M. Barth , Ely K. Tsern , Mark A. Horowitz , Donald C. Stark , Craig E. Hampel , Frederick A. Ware , John B. Dillon , by Nancy David Dillon
IPC分类号： G06F1200
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076
摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.

4. 发明授权

US08918703B2 Memory system with error detection and retry modes of operation 有权
标题翻译：具有错误检测和重试操作模式的内存系统
公开(公告)号：US08918703B2
公开(公告)日：2014-12-23
申请号：US13730942
申请日：2012-12-29
申请人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
发明人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC分类号： G11C29/00 , H03M13/00 , G06F11/10 , G06F11/14 , H04L1/00 , H04L1/08 , H04L1/18 , G06F11/00
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
摘要翻译：存储器系统包括具有至少一个信号线的链路和控制器。所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。至少一个接收器耦合到链路以接收第二数据。第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

5. 发明申请

US20130139032A1 Memory System With Error Detection And Retry Modes Of Operation 有权
公开(公告)号：US20130139032A1
公开(公告)日：2013-05-30
申请号：US13730942
申请日：2012-12-29
申请人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
发明人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC分类号： G06F11/10 , G06F11/00
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.

6. 发明授权

US07831882B2 Memory system with error detection and retry modes of operation 有权
标题翻译：具有错误检测和重试操作模式的内存系统
公开(公告)号：US07831882B2
公开(公告)日：2010-11-09
申请号：US11145429
申请日：2005-06-03
申请人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
发明人： Ely K. Tsern , Mark A. Horowitz , Frederick A. Ware
IPC分类号： H03M13/00 , G11C13/00
CPC分类号： G06F11/073 , G06F3/0619 , G06F3/064 , G06F3/0673 , G06F11/006 , G06F11/0745 , G06F11/0766 , G06F11/0793 , G06F11/10 , G06F11/1008 , G06F11/1068 , G06F11/1076 , G06F11/1402 , G06F11/141 , G06F11/1443 , G06F11/20 , G11C29/52 , H03M13/03 , H04L1/0057 , H04L1/0061 , H04L1/08 , H04L1/1809
摘要： A memory system includes a link having at least one signal line and a controller. The controller includes at least one transmitter coupled to the link to transmit first data, and a first error protection generator coupled to the transmitter. The first error protection generator dynamically adds an error detection code to at least a portion of the first data. At least one receiver is coupled to the link to receive second data. A first error detection logic determines if the second data received by the controller contains at least one error and, if an error is detected, asserts a first error condition. The system includes a memory device having at least one memory device transmitter coupled to the link to transmit the second data. A second error protection generator coupled to the memory device transmitter dynamically adds an error detection code to at least a portion of the second data.
摘要翻译：存储器系统包括具有至少一个信号线的链路和控制器。所述控制器包括耦合到所述链路以发送第一数据的至少一个发射机，以及耦合到所述发射机的第一误差保护发生器。第一错误保护发生器动态地将错误检测码添加到第一数据的至少一部分。至少一个接收器耦合到链路以接收第二数据。第一错误检测逻辑确定控制器接收到的第二数据是否包含至少一个错误，并且如果检测到错误则断言第一错误状况。该系统包括具有耦合到链路以传输第二数据的至少一个存储器件发送器的存储器件。耦合到存储器件发射器的第二误差保护发生器动态地将错误检测码添加到第二数据的至少一部分。

7. 发明授权

US06718431B2 Apparatus and method for pipelined memory operations 失效
标题翻译：流水线存储器操作的装置和方法
公开(公告)号：US06718431B2
公开(公告)日：2004-04-06
申请号：US10053632
申请日：2002-01-18
申请人： Richard M. Barth , Ely K. Tsern , Mark A. Horowitz , Donald C. Stark , Craig E. Hampel , Frederick A. Ware , John B. Dillon
发明人： Richard M. Barth , Ely K. Tsern , Mark A. Horowitz , Donald C. Stark , Craig E. Hampel , Frederick A. Ware , John B. Dillon
IPC分类号： G06F1200
CPC分类号： G11C7/1006 , G06F13/1615 , G11C7/10 , G11C7/1039 , G11C8/12 , G11C11/4076
摘要： A memory device has interface circuitry and a memory core which make up the stages of a pipeline, each stage being a step in a universal sequence associated with the memory core. The memory device has a plurality of operation units such as precharge, sense, read and write, which handle the primitive operations of the memory core to which the operation units are coupled. The memory device further includes a plurality of transport units configured to obtain information from external connections specifying an operation for one of the operation units and to transfer data between the memory core and the external connections. The transport units operate concurrently with the operation units as added stages to the pipeline, thereby creating a memory device which operates at high throughput and with low service times under the memory reference stream of common applications.
摘要翻译：存储器设备具有构成流水线阶段的接口电路和存储器核心，每个阶段是与存储器核心相关联的通用序列中的步骤。存储装置具有多个操作单元，例如预充电，感测，读取和写入，其处理操作单元耦合到的存储器核的原始操作。存储装置还包括多个传输单元，其被配置为从外部连接获取信息，指定操作单元之一的操作并且在存储器核心和外部连接之间传送数据。运输单元与运营单元同时运行作为流水线的附加阶段，从而创建一种在普通应用的存储器参考流下以高吞吐量和低服务时间运行的存储器件。

8. 发明授权

US08756395B2 Controlling DRAM at time DRAM ready to receive command when exiting power down 有权
标题翻译：在DRAM时刻控制DRAM，准备在断电时接收命令
公开(公告)号：US08756395B2
公开(公告)日：2014-06-17
申请号：US13406465
申请日：2012-02-27
申请人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
发明人： Richard M. Barth , Ely K. Tsern , Craig E. Hampel , Frederick A. Ware , Todd W. Bystrom , Bradley A. May , Paul G. Davis
IPC分类号： G06F13/00
CPC分类号： G11C7/1072 , G06F1/3225 , G06F13/1689 , G06F13/1694 , G06F13/4239 , G11C7/20 , G11C8/12 , G11C11/4072 , G11C11/4074 , G11C11/4076 , G11C2207/2227 , G11C2207/2254 , Y02D10/151
摘要： Methods of operation of a memory device and system are provided in embodiments. Initialization operations are conducted at a first frequency of operation during an initialization sequence. Memory access operations are then performed at a second frequency of operation. The second frequency of operation is higher than the first frequency of operation. Also, the memory access operations include a read operation and a write operation. In an embodiment, information that represents the first frequency of operation and the second frequency of operation is read from a serial presence detect device.
摘要翻译：在实施例中提供了存储器件和系统的操作方法。初始化操作在初始化序列期间以第一操作频率进行。然后在第二操作频率下执行存储器存取操作。第二个操作频率高于第一个操作频率。此外，存储器访问操作包括读取操作和写入操作。在实施例中，从串行存在检测装置读取表示第一操作频率和第二操作频率的信息。

9. 发明授权

US08320202B2 Clocked memory system with termination component 有权
标题翻译：带终端组件的定时存储系统
公开(公告)号：US08320202B2
公开(公告)日：2012-11-27
申请号：US11767983
申请日：2007-06-25
申请人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
发明人： Frederick A. Ware , Ely K. Tsern , Richard E. Perego , Craig E. Hampel
IPC分类号： G11C7/00
CPC分类号： G11C7/1039 , G11C5/04 , G11C5/063 , G11C7/1048
摘要： A memory system having first and second memory devices and a termination component. A first signal line is coupled to the first memory device to provide first data, associated with a write command, to the first memory device, and a second signal line coupled to the second memory device to provide second data, associated with the write command, to the second memory device. A control signal path is coupled to the first and second memory devices and the termination component such that the write command propagating on the control signal path propagates past the first memory device and the second memory device before reaching the termination component. A third signal line is provided to convey a clock signal that indicates when the write command propagating on the control signal path is to be sampled by the first and second memory devices.
摘要翻译：一种具有第一和第二存储器件和终端部件的存储器系统。第一信号线耦合到第一存储器设备，以向第一存储器设备提供与写命令相关联的第一数据，以及耦合到第二存储器设备以提供与写命令相关联的第二数据的第二信号线，到第二存储设备。控制信号路径被耦合到第一和第二存储器件和终端部件，使得在到达终端部件之前，在控制信号路径上传播的写入命令传播通过第一存储器件和第二存储器件。提供第三信号线来传送时钟信号，该时钟信号指示在控制信号路径上传播的写入命令何时被第一和第二存储器件采样。

10. 发明申请

US20100061047A1 Upgradable Memory System with Reconfigurable Interconnect 有权
标题翻译：可重构互连的可升级内存系统
公开(公告)号：US20100061047A1
公开(公告)日：2010-03-11
申请号：US12538613
申请日：2009-08-10
申请人： Richard E. Perego , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
发明人： Richard E. Perego , Frederick A. Ware , Ely K. Tsern , Craig E. Hampel
IPC分类号： G06F1/16
CPC分类号： G06F13/409 , G11C5/04 , G11C2207/105 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14 , Y02D10/151
摘要： Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.
摘要翻译：描述的是采用可配置的片上终端元件的系统，其允许用户从两个或多个端接拓扑中进行选择。一个拓扑结构可编程，以支持轨到轨或半电源终端。另一种拓扑选择性地包括固定或可变滤波器元件，从而允许针对不同级别的速度性能和功耗来调整终端特性。终端电压和阻抗也可能会被调整。

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