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1. 发明授权

US07688925B2 Bit-deskewing IO method and system 有权
标题翻译：位偏移IO方法和系统
公开(公告)号：US07688925B2
公开(公告)日：2010-03-30
申请号：US11195082
申请日：2005-08-01
申请人： Edward Lee , Arvind Bomdica , Lin Chen , Claude Gauthier , Sam Huynh , Hiok-Tiaq Ng , John Ling , Jennifer Ho , Siji Menokki Kandiyil , Gin Yee , Joseph Macri
发明人： Edward Lee , Arvind Bomdica , Lin Chen , Claude Gauthier , Sam Huynh , Hiok-Tiaq Ng , John Ling , Jennifer Ho , Siji Menokki Kandiyil , Gin Yee , Joseph Macri
IPC分类号： H04L7/00
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0805 , H04L7/0004 , H04L7/0037 , H04L7/0337
摘要： An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.
摘要翻译：描述了用于位移校正的IO方法和系统。实施例包括具有在其间传送数据的多个组件的计算机系统。在一个实施例中，系统组件从发送组件接收正向选通信号和多个数据位信号。接收组件包括可选择对准前向选通采样时钟以提高采样精度的正向选通时钟恢复电路。接收组件还包括至少一个数据比特时钟恢复电路，可配置为对准数据比特采样时钟，以提高采样精度，并接收来自正向选通时钟恢复电路的信号，使得数据比特采样时钟跟踪系统运行期间的正向选通采样时钟。

2. 发明申请

US20070036020A1 Bit-deskewing IO method and system 有权
标题翻译：位偏移IO方法和系统
公开(公告)号：US20070036020A1
公开(公告)日：2007-02-15
申请号：US11195082
申请日：2005-08-01
申请人： Edward Lee , Arvind Bomdica , Lin Chen , Claude Gauthier , Sam Huynh , Hiok-Tiaq Ng , John Ling , Jennifer Ho , Siji M.K. , Gin Yee , Joseph Macri
发明人： Edward Lee , Arvind Bomdica , Lin Chen , Claude Gauthier , Sam Huynh , Hiok-Tiaq Ng , John Ling , Jennifer Ho , Siji M.K. , Gin Yee , Joseph Macri
IPC分类号： G11C8/00
CPC分类号： H03L7/0814 , H03L7/07 , H03L7/0805 , H04L7/0004 , H04L7/0037 , H04L7/0337
摘要： An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmitting component. The receiving component includes a forward strobe clock recovery circuit configurable to align a forward strobe sampling clock so as to improve sampling accuracy. The receiving component further includes at least one data bit clock recovery circuit configurable to align a data bit sampling clock so as to improve sampling accuracy, and to receive a signal from the forward strobe clock recovery circuit that causes the data bit sampling clock to track the forward strobe sampling clock during system operation.
摘要翻译：描述了用于位移校正的IO方法和系统。实施例包括具有在其间传送数据的多个组件的计算机系统。在一个实施例中，系统组件从发送组件接收正向选通信号和多个数据位信号。接收组件包括可选择对准前向选通采样时钟以提高采样精度的正向选通时钟恢复电路。接收组件还包括至少一个数据比特时钟恢复电路，可配置为对准数据比特采样时钟，以提高采样精度，并接收来自正向选通时钟恢复电路的信号，使得数据比特采样时钟跟踪系统运行期间的正向选通采样时钟。

3. 发明申请

US20070288781A1 Low power mode unipolar current/voltage mode interface 有权
标题翻译：低功耗模式单极性电流/电压模式接口
公开(公告)号：US20070288781A1
公开(公告)日：2007-12-13
申请号：US11732783
申请日：2007-04-03
申请人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
发明人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.
摘要翻译：描述用于存储器接口的功耗降低过程的实施例。电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

4. 发明申请

US20070098163A1 Error detection in high-speed asymmetric interfaces 有权
标题翻译：高速非对称接口中的错误检测
公开(公告)号：US20070098163A1
公开(公告)日：2007-05-03
申请号：US11592074
申请日：2006-11-01
申请人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
IPC分类号： H04N7/167
CPC分类号： G06F11/10
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速非对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。所接收的签名与由第一组件存储的签名进行比较。两个签名对应于接口上的事务。基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

5. 发明申请

US20090125747A1 Asymmetrical IO Method and System 有权
标题翻译：非对称IO方法和系统
公开(公告)号：US20090125747A1
公开(公告)日：2009-05-14
申请号：US12356804
申请日：2009-01-21
申请人： Stephen Morein , Joseph Macri , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Stephen Morein , Joseph Macri , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F1/12
CPC分类号： H04L7/02 , H04L7/0025 , H04L7/0091
摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.
摘要翻译：描述了非对称IO方法和系统。在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。共享资源包括一个共享相位内插器。在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

6. 发明授权

US07509515B2 Method and system for communicated client phase information during an idle period of a data bus 有权
标题翻译：在数据总线空闲期间传送的客户端相位信息的方法和系统
公开(公告)号：US07509515B2
公开(公告)日：2009-03-24
申请号：US11231193
申请日：2005-09-19
申请人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F1/00
CPC分类号： G06F1/04 , G06F1/10 , H04L7/0012 , H04L7/033
摘要： A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.
摘要翻译：描述了通过双向数据链路将客户端相位信息发送到主机设备的系统和方法。实施例包括相对于通过双向数据链路在主机设备和客户端设备之间传输的数据信号检测时钟信号的相位。数据链路包括一个或多个数据线，每个数据线被配置为传送数据信号的相应位。该相位被编码为客户端相位信息，并通过一个或多个数据线在主机和客户端设备之间传输。客户端相位信息是在数据链路上的读取和写入操作之间的双向数据链路的电气周转时间周期期间发送的。

7. 发明授权

US08661300B1 Error detection in high-speed asymmetric interfaces 有权
标题翻译：高速非对称接口中的错误检测
公开(公告)号：US08661300B1
公开(公告)日：2014-02-25
申请号：US13169977
申请日：2011-06-27
申请人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F11/00
CPC分类号： G06F11/10
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速非对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。所接收的签名与由第一组件存储的签名进行比较。两个签名对应于接口上的事务。基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

8. 发明授权

US07487378B2 Asymmetrical IO method and system 有权
标题翻译：非对称IO方法和系统
公开(公告)号：US07487378B2
公开(公告)日：2009-02-03
申请号：US11231078
申请日：2005-09-19
申请人： Stephen Morein , Joseph Macri , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Stephen Morein , Joseph Macri , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F1/04 , G06F1/24 , G06F11/00
CPC分类号： H04L7/02 , H04L7/0025 , H04L7/0091
摘要： An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines between the host and client are also used to transmit phase information from the client device to the host device, obviating the need for additional, dedicated lines or pins.
摘要翻译：描述了非对称IO方法和系统。在一个实施例中，主机设备包括用于主机设备和客户端设备的数据同步的共享资源。共享资源包括一个共享相位内插器。在一个实施例中，主机和客户机之间的数据线也用于将相位信息从客户端设备发送到主机设备，从而避免了对额外的专用线或引脚的需要。

9. 发明申请

US20070067661A1 Communicating client phase information in an IO system 有权
标题翻译：在IO系统中沟通客户端阶段信息
公开(公告)号：US20070067661A1
公开(公告)日：2007-03-22
申请号：US11231193
申请日：2005-09-19
申请人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
IPC分类号： G06F1/04
CPC分类号： G06F1/04 , G06F1/10 , H04L7/0012 , H04L7/033
摘要： A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.
摘要翻译：描述了通过双向数据链路将客户端相位信息发送到主机设备的系统和方法。实施例包括相对于通过双向数据链路在主机设备和客户端设备之间传输的数据信号检测时钟信号的相位。数据链路包括一个或多个数据线，每个数据线被配置为传送数据信号的相应位。该相位被编码为客户端相位信息，并通过一个或多个数据线在主机和客户端设备之间传输。客户端相位信息是在数据链路上的读取和写入操作之间的双向数据链路的电气周转时间周期期间传送的。

10. 发明授权

US08892963B2 Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines 有权
标题翻译：使用专用接口线路的高速非对称接口中的错误检测
公开(公告)号：US08892963B2
公开(公告)日：2014-11-18
申请号：US11595619
申请日：2006-11-09
申请人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F11/00 , H04L1/00 , G06F11/10 , G06F11/08
CPC分类号： H04L1/0045 , G06F11/08 , G06F11/10 , H04L1/0061 , H04L2001/0094
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速非对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。第一个组件通过接口的READ和WRITE操作同时从一个接口的一行接收第二个组件的签名。与从第二组件到第一组件的签名传输相关联的延迟是第二组件计算签名所花费的时间。所接收的签名与由第一组件存储的签名进行比较。两个签名对应于特定的READ或WRITE命令。基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

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