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1. 发明授权

US07509515B2 Method and system for communicated client phase information during an idle period of a data bus 有权
标题翻译：在数据总线空闲期间传送的客户端相位信息的方法和系统
公开(公告)号：US07509515B2
公开(公告)日：2009-03-24
申请号：US11231193
申请日：2005-09-19
申请人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
发明人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju E. Lee , Lin Chen
IPC分类号： G06F1/00
CPC分类号： G06F1/04 , G06F1/10 , H04L7/0012 , H04L7/033
摘要： A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a bidirectional data link. The data link includes one or more data lines each configured to transmit a corresponding bit of the data signal. The phase is encoded as client phase information and transmitted between the host and client device over the one or more data lines. The client phase information is transmitted during an electrical turnaround time period of the bidirectional data link between a read and write operation over the data link.
摘要翻译：描述了通过双向数据链路将客户端相位信息发送到主机设备的系统和方法。实施例包括相对于通过双向数据链路在主机设备和客户端设备之间传输的数据信号检测时钟信号的相位。数据链路包括一个或多个数据线，每个数据线被配置为传送数据信号的相应位。该相位被编码为客户端相位信息，并通过一个或多个数据线在主机和客户端设备之间传输。客户端相位信息是在数据链路上的读取和写入操作之间的双向数据链路的电气周转时间周期期间发送的。

2. 发明授权

US06476811B1 Method and apparatus for compressing parameter values for pixels in a display frame 有权
标题翻译：用于压缩显示帧中的像素的参数值的方法和装置
公开(公告)号：US06476811B1
公开(公告)日：2002-11-05
申请号：US09387870
申请日：1999-09-01
申请人： John E. DeRoo , Steven Morein , Brian Favela , Michael T. Wright
发明人： John E. DeRoo , Steven Morein , Brian Favela , Michael T. Wright
IPC分类号： G06T1500
CPC分类号： G06T9/00
摘要： A method and apparatus for compressing parameter values for pixels within a frame is accomplished by first grouping pixels in the display frame into a plurality of pixel blocks, where each pixel block includes a plurality of pixels. For at least one of the pixel blocks, the parameter values for the pixel block are translated into a column-wise differential slope representation that represents the parameter values as a plurality of reference points, a plurality of slopes, and a plurality of slope differentials. The column-wise differential slope representation is then transformed into a planar differential slope representation that reduces the representation of the plurality of reference points and the plurality of slopes to a single reference pixel value, two reference slopes, and a plurality of slope differentials. An output format representation of the planar differential slope representation is then generated, where encoding of the slope differentials allows the parameter values for the pixel block to be compressed. This compressed format representation of the parameter values can then be stored in and retrieved from memory.
摘要翻译：通过首先将显示帧中的像素分组为多个像素块来实现用于压缩帧内的像素的参数值的方法和装置，其中每个像素块包括多个像素。对于像素块中的至少一个，像素块的参数值被转换为逐列的差分斜率表示，其表示参数值作为多个参考点，多个斜率和多个斜率差。然后，逐列差分斜率表示被转换成平面差分斜率表示，其将多个参考点和多个斜率的表示减少到单个参考像素值，两个参考斜率和多个斜率差。然后生成平面差分斜率表示的输出格式表示，其中斜率差的编码允许压缩像素块的参数值。然后可以将参数值的这种压缩格式表示存储在存储器中并从存储器中检索。

3. 发明申请

US20080005455A1 Fast transition from low-speed mode to high-speed mode in high-speed interfaces 有权
标题翻译：在高速接口中从低速模式快速转换到高速模式
公开(公告)号：US20080005455A1
公开(公告)日：2008-01-03
申请号：US11804413
申请日：2007-05-17
申请人： Joseph Macri , Steven Morein , Ming-Ju Lee , Lin Chen
发明人： Joseph Macri , Steven Morein , Ming-Ju Lee , Lin Chen
IPC分类号： G06F12/08 , G06F1/12
CPC分类号： G06F1/3275 , G06F1/3225 , G11C7/1045 , G11C7/22 , G11C7/222 , G11C11/4076 , G11C2207/2227 , Y02D10/14
摘要： Embodiments directed to a memory device and a memory controller that continue to operate in a low-power mode during the period required for analog timing circuitry to initialize and become usable, are described. During a low-speed to high-speed transition mode of operation for a high-speed interface, timing circuitry of the interface between the memory device and memory controller locks to a forward clock signal concurrent with the continued operation of the interface in low-speed mode. A reference clock signal configured to operate at a rate that provides both a high-speed mode and a low-speed mode and which is used as a single rate clock allows phase detection and correction circuitry to be disabled, thus allowing the idle period caused by a transition from low-speed mode to high-speed mode to be significantly reduced.
摘要翻译：描述了在模拟定时电路初始化和变得可用的时间段期间继续在低功率模式下工作的存储器件和存储器控制器的实施例。在用于高速接口的低速到高速转换操作模式期间，存储器件和存储器控制器之间的接口的定时电路锁定到正向时钟信号，并且与低速接口的继续操作同时进行模式。参考时钟信号被配置为以提供高速模式和低速模式并且被用作单个速率时钟的速率操作，允许相位检测和校正电路被禁用，从而允许由从低速模式向高速模式的转变将大大降低。

4. 发明申请

US20070285427A1 GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER 审中-公开
标题翻译：图形处理结构使用统一的阴影
公开(公告)号：US20070285427A1
公开(公告)日：2007-12-13
申请号：US11842256
申请日：2007-08-21
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06F15/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译：公开了一种采用单一着色器的图形处理架构。该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一多个输入之一。着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器在音序器中

5. 发明申请

US20100231592A1 GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER 审中-公开
标题翻译：图形处理结构使用统一的阴影
公开(公告)号：US20100231592A1
公开(公告)日：2010-09-16
申请号：US12791597
申请日：2010-06-01
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06F15/00 , G06T15/50
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译：公开了一种采用单一着色器的图形处理架构。该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一多个输入之一。着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器在音序器中

6. 发明授权

US07327369B2 Graphics processing architecture employing a unified shader 有权
标题翻译：采用统一着色器的图形处理架构
公开(公告)号：US07327369B2
公开(公告)日：2008-02-05
申请号：US11117863
申请日：2005-04-29
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06F15/00 , G06T1/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译：公开了一种采用单一着色器的图形处理架构。该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的一个输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作执行所述顶点操作或像素操作之一多个输入之一。着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器在音序器中

7. 发明申请

US20070288781A1 Low power mode unipolar current/voltage mode interface 有权
标题翻译：低功耗模式单极性电流/电压模式接口
公开(公告)号：US20070288781A1
公开(公告)日：2007-12-13
申请号：US11732783
申请日：2007-04-03
申请人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
发明人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.
摘要翻译：描述用于存储器接口的功耗降低过程的实施例。电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

8. 发明申请

US20050110792A1 GRAPHICS PROCESSING ARCHITECTURE EMPLOYING A UNIFIED SHADER 有权
标题翻译：图形处理结构使用统一的阴影
公开(公告)号：US20050110792A1
公开(公告)日：2005-05-26
申请号：US10718318
申请日：2003-11-20
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06T15/00 , G06T15/80 , G06T1/00 , G06F15/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.
摘要翻译：公开了一种采用单一着色器的图形处理架构。该架构包括响应于控制信号选择多个输入中的一个的电路; 以及耦合到所述仲裁器的着色器，用于处理所述多个输入中的所选择的输入，所述着色器包括用于执行顶点操作和像素操作的装置，并且其中所述着色器基于所选择的所述操作来执行所述顶点操作或像素操作之一多个输入之一。着色器包括用于存储多个所选择的输入的寄存器块，保持顶点操作和像素操作指令的定序器以及能够响应于所保持的指令对所选择的输入执行浮点运算和逻辑运算的处理器在音序器中

9. 发明授权

US06897871B1 Graphics processing architecture employing a unified shader 有权
公开(公告)号：US06897871B1
公开(公告)日：2005-05-24
申请号：US10718318
申请日：2003-11-20
申请人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
发明人： Steven Morein , Laurent Lefebvre , Andy Gruber , Andi Skende
IPC分类号： G06T15/00 , G06T15/80 , G06F15/00 , G06T1/00
CPC分类号： G06T1/20 , G06T15/005 , G06T15/80
摘要： A graphics processing architecture employing a single shader is disclosed. The architecture includes a circuit operative to select one of a plurality of inputs in response to a control signal; and a shader, coupled to the arbiter, operative to process the selected one of the plurality of inputs, the shader including means for performing vertex operations and pixel operations, and wherein the shader performs one of the vertex operations or pixel operations based on the selected one of the plurality of inputs. The shader includes a register block which is used to store the plurality of selected inputs, a sequencer which maintains vertex manipulation and pixel manipulations instructions and a processor capable of executing both floating point arithmetic and logical operations on the selected inputs in response to the instructions maintained in the sequencer.

10. 发明授权

US06433788B1 Dual fragment-cache pixel processing circuit and method therefore 失效
标题翻译：双片段缓存像素处理电路和方法因此
公开(公告)号：US06433788B1
公开(公告)日：2002-08-13
申请号：US09364442
申请日：1999-07-30
申请人： Steven Morein
发明人： Steven Morein
IPC分类号： G06F1516
CPC分类号： G06T1/60
摘要： A dual-cache pixel processing circuit that allows one cache to be flushed while the other receives subsequent pixel fragments is presented. The system includes a first fragment cache and a first set of state registers where the first set of state registers stores state variables for drawing operations corresponding to fragments stored in the first fragment cache. The system also includes a second fragment cache and a second set of state registers where the second set of state registers stores state variables for drawing operations corresponding to fragments stored in the second fragment cache. The system further includes a render backend block that is operably coupled to the first and second fragment caches and to a frame buffer that stores current pixel information for a plurality of pixels in a display frame. The render backend block combines fragments received from the first and second caches with portions of the current pixel information in the frame buffer to produce revised pixel information that is stored back in the frame buffer. The combination operations performed by the render backend block utilize the state information stored in one of the first and second sets of state registers based on from which fragment cache the fragment being combined originated. A control block that is operably coupled to the first and second fragment caches and the first and second sets of state registers initially routes received fragments to the first fragment cache. When a state change occurs, the control block alters the flow of fragments such that subsequent fragments are routed to the second fragment cache while the first fragment cache is flushed. Flushing the first fragment cache includes providing all of the pixel fragments included in the first fragment cache to the render backend block along with the old state variables that are stored in the first set of state registers.
摘要翻译：呈现双缓冲像素处理电路，其允许一个高速缓存被冲洗，而另一个缓存则接收后续的像素片段。该系统包括第一片段高速缓存和第一组状态寄存器，其中第一组状态寄存器存储用于对应于存储在第一片段高速缓存中的片段的绘图操作的状态变量。该系统还包括第二片段缓存和第二组状态寄存器，其中第二组状态寄存器存储与存储在第二片段高速缓存中的片段相对应的绘图操作的状态变量。该系统还包括可操作地耦合到第一和第二片段高速缓存的渲染后端块和存储显示帧中的多个像素的当前像素信息的帧缓冲器。渲染后端块将从第一和第二高速缓存接收到的片段与帧缓冲器中的当前像素信息的部分组合，以产生被重新存储在帧缓冲器中的修正像素信息。由渲染后端块执行的组合操作利用存储在第一和第二组状态寄存器之一中的状态信息，该状态信息基于从哪个片段缓存组合起始。可操作地耦合到第一和第二片段高速缓存以及第一和第二状态寄存器组的控制块首先将接收到的片段路由到第一片段高速缓存。当发生状态改变时，控制块改变片段的流程，使得在刷新第一片段高速缓存的同时将后续片段路由到第二片段高速缓存。刷新第一片段高速缓存包括将包含在第一片段高速缓存中的所有像素片段与存储在第一组状态寄存器中的旧状态变量一起提供给渲染后端块。

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