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1. 发明申请

US20130321619A1 ELECTRONIC DEVICE WITH DISTANCE MEASURING FUNCTION AND METHOD THEREOF 审中-公开
标题翻译：具有距离测量功能的电子设备及其方法
公开(公告)号：US20130321619A1
公开(公告)日：2013-12-05
申请号：US13584770
申请日：2012-08-13
申请人： MING-JU LEE
发明人： MING-JU LEE
IPC分类号： H04N7/18
CPC分类号： G01C3/32 , G01C3/08
摘要： A method for measuring distance includes: obtaining an image of an object and detecting whether the image of the object is clear when a camera module is initialed to capture the image of the object; controlling a lens to move along a center axis of the lens barrel when detecting the image of the object is not clear, and controlling the lens to stop moving when detecting the image of the object is clear; obtaining an image distance variation, and calculates a current image distance according to the image distance variation and a initial image distance; calculating a current object distance according to the current image distance, a focal distance, and a formula 1/u=1/f-1/v, wherein, u is the current objection distance, f is the focal distance, v is the current image distance.
摘要翻译：用于测量距离的方法包括：当相机模块被初始化以捕获对象的图像时，获得对象的图像并检测对象的图像是否清晰; 当检测到物体的图像时，控制透镜沿着镜筒的中心轴移动是不清楚的，并且当检测到物体的图像时控制透镜停止移动是清楚的; 获得图像距离变化，并根据图像距离变化和初始图像距离计算当前图像距离; 根据当前图像距离，焦距和公式1 / u = 1 / f-1 / v计算当前物体距离，其中，u是当前对象距离，f是焦距，v是电流图像距离。

2. 发明授权

US07999595B2 Rectifying and level shifting circuit 有权
标题翻译：整流和电平转换电路
公开(公告)号：US07999595B2
公开(公告)日：2011-08-16
申请号：US12560991
申请日：2009-09-16
申请人： Jinyung Namkoong , Arvind Bomdica , Ming-Ju Lee
发明人： Jinyung Namkoong , Arvind Bomdica , Ming-Ju Lee
IPC分类号： G03L5/00
CPC分类号： H03K19/018528
摘要： A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs.
摘要翻译：电路包括具有至少两个输入的差分电路，第一可变阻抗电路和第二可变阻抗电路。第一可变阻抗电路在差分电路的第一分支和输出之间。第一可变阻抗电路提供第一可变阻抗。第二可变阻抗电路在差分电路的第二分支和输出之间。第二可变阻抗电路提供第二可变阻抗。第一可变阻抗和第二可变阻抗根据两个输入之间的电压差而变化。

3. 发明申请

US20070288781A1 Low power mode unipolar current/voltage mode interface 有权
标题翻译：低功耗模式单极性电流/电压模式接口
公开(公告)号：US20070288781A1
公开(公告)日：2007-12-13
申请号：US11732783
申请日：2007-04-03
申请人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
发明人： Joseph Macri , Steven Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
IPC分类号： G06F1/00
CPC分类号： G06F1/3203 , G06F1/3253 , Y02D10/151 , Y02D50/20
摘要： Embodiments of a power consumption reduction process for memory interfaces are described. A power management process reduces the amount of time that current flows in a high or low terminated, current or voltage mode unipolar bus interface by reducing the amount of time the bus remains in a logic state that requires current flow.
摘要翻译：描述用于存储器接口的功耗降低过程的实施例。电源管理过程通过减少总线保持在需要电流的逻辑状态的时间量，减少电流在高或低端接，电流或电压模式单极总线接口中流动的时间。

4. 发明申请

US20070098163A1 Error detection in high-speed asymmetric interfaces 有权
标题翻译：高速非对称接口中的错误检测
公开(公告)号：US20070098163A1
公开(公告)日：2007-05-03
申请号：US11592074
申请日：2006-11-01
申请人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
IPC分类号： H04N7/167
CPC分类号： G06F11/10
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component controls many operations of the second component, including receiving a signature from the second component over an existing line of the interface. The signature received is compared to a signature stored by the first component. Both signatures correspond to a transaction over the interface. Based on the comparison, the first component determines whether the transaction was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速非对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。第一个组件控制第二个组件的许多操作，包括通过接口的现有行接收来自第二个组件的签名。所接收的签名与由第一组件存储的签名进行比较。两个签名对应于接口上的事务。基于比较，第一个组件确定事务是否成功，并根据需要引导第二个组件。

5. 发明申请

US20070038789A1 Dynamic bus inversion method and system 有权
标题翻译：动态总线反演方法及系统
公开(公告)号：US20070038789A1
公开(公告)日：2007-02-15
申请号：US11357291
申请日：2006-02-17
申请人： Joseph Macri , Stephen Morein , Ming-Ju Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Ming-Ju Lee , Lin Chen
IPC分类号： G06F13/42
CPC分类号： H04L25/4915 , H03L7/07 , H03L7/0805 , H03L7/0814 , H04L7/0004 , H04L7/0008 , H04L7/0037 , H04L7/0337
摘要： A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits that will be transitioning to a new value. If it is determined that the bus is to be inverted, the transmitter encodes a DBI signal on a shared line of the bus. In an embodiment, the shared line is used for different purposes at different times, obviating the need for a dedicated line or pin for the encoded DBI signal. The receiver receives and decodes the DBI signal and, in response, appropriately decodes the received data.
摘要翻译：描述了动态总线反演（DBI）方法和系统。在各种实施例中，发射机通过多比特高速总线向接收机发送数据。在一个实施例中，发射机基于将要转换到新值的数据比特数来确定是否反转总线。如果确定总线被反相，则发送器对总线的共享线路上的DBI信号进行编码。在一个实施例中，共享线路在不同时间用于不同的目的，从而避免了对编码的DBI信号的专用线路或引脚的需要。接收器接收并解码DBI信号，作为响应，对接收到的数据进行适当的解码。

6. 发明申请

US20110063010A1 RECTIFYING AND LEVEL SHIFTING CIRCUIT 有权
标题翻译：整流和电平转换电路
公开(公告)号：US20110063010A1
公开(公告)日：2011-03-17
申请号：US12560991
申请日：2009-09-16
申请人： Jinyung Namkoong , Arvind Bomdica , Ming-Ju Lee
发明人： Jinyung Namkoong , Arvind Bomdica , Ming-Ju Lee
IPC分类号： H03L5/00
CPC分类号： H03K19/018528
摘要： A circuit includes a differential circuit having at least to two inputs, a first variable impedance circuit, and a second variable impedance circuit. The first variable impedance circuit is between a first branch of the differential circuit and an output. The first variable impedance circuit provides a first variable impedance. The a second variable impedance circuit is between a second branch of the differential circuit and the output. The second variable impedance circuit provides a second variable impedance. The first variable impedance and the second variable impedance vary in accordance with a voltage difference between the two inputs.
摘要翻译：电路包括具有至少两个输入的差分电路，第一可变阻抗电路和第二可变阻抗电路。第一可变阻抗电路在差分电路的第一分支和输出之间。第一可变阻抗电路提供第一可变阻抗。第二可变阻抗电路在差分电路的第二分支和输出之间。第二可变阻抗电路提供第二可变阻抗。第一可变阻抗和第二可变阻抗根据两个输入之间的电压差而变化。

7. 发明授权

US07714615B2 De-emphasis circuit for a voltage mode driver used to communicate via a differential communication link 有权
标题翻译：用于通过差分通信链路进行通信的电压模式驱动器的去加重电路
公开(公告)号：US07714615B2
公开(公告)日：2010-05-11
申请号：US12032741
申请日：2008-02-18
申请人： Yikai Liang , Arvind Bomdica , Min Xu , Ming-Ju Lee
发明人： Yikai Liang , Arvind Bomdica , Min Xu , Ming-Ju Lee
IPC分类号： H03K19/094
CPC分类号： H03K19/0019 , H04L1/08 , H04L25/0272 , H04L25/0286
摘要： A circuit for de-emphasizing information transmitted via a differential communication link includes a voltage mode differential circuit and a bi-directional current source circuit. The voltage mode differential circuit includes a first and second output terminal. The voltage mode differential circuit provides a first voltage via the first output terminal and second voltage via the second output terminal in response to a differential input voltage. The bi-directional current source circuit is operatively coupled between the first and second terminals. The bi-directional current source circuit selectively provides current in a first and second direction between the first and second terminals based on the first and second voltage.
摘要翻译：用于去强调通过差分通信链路发送的信息的电路包括电压模式差分电路和双向电流源电路。电压模式差分电路包括第一和第二输出端子。电压模式差分电路响应于差分输入电压经由第一输出端经第二输出端提供第一电压和第二电压。双向电流源电路可操作地耦合在第一和第二端子之间。双向电流源电路基于第一和第二电压选择性地在第一和第二端子之间的第一和第二方向上提供电流。

8. 发明授权

US08482165B2 Voice coil motor housing and voice coil motor using same 失效
标题翻译：音圈电机外壳和音圈电机使用相同
公开(公告)号：US08482165B2
公开(公告)日：2013-07-09
申请号：US13214262
申请日：2011-08-22
申请人： Mao-Kuo Hsu , Ming-Ju Lee
发明人： Mao-Kuo Hsu , Ming-Ju Lee
IPC分类号： H02K41/03
CPC分类号： H02K41/0356
摘要： A voice coil motor housing includes a top wall having an opening and four sidewalls extending from the top wall. The four sidewalls and the top wall cooperatively form a rectangular chamber opened at one end. Each of the sidewalls includes a top portion and a bottom portion. The top portions of the four sidewalls are connected to one another and forming a substantially gapless seam between each two adjacent sidewalls at the top portions. At least one slot is defined in the bottom portions of the sidewalls, the at least one slot is perpendicular to the top wall, and the slot is arranged adjacent to the corresponding gapless seam. At least one snap is arranged on the sidewalls at the corresponding bottom portion thereof, and the at least one snap protrudes inwardly of the chamber.
摘要翻译：音圈马达壳体包括具有开口的顶壁和从顶壁延伸的四个侧壁。四个侧壁和顶壁协同地形成在一端开口的矩形室。每个侧壁包括顶部和底部。四个侧壁的顶部彼此连接并且在顶部部分的每两个相邻侧壁之间形成基本上无间隙的接缝。至少一个狭槽限定在侧壁的底部中，至少一个狭槽垂直于顶壁，并且狭槽被布置成与相应的无间隙接缝相邻。至少一个卡扣布置在其对应底部的侧壁上，并且至少一个卡扣突出到该腔室的内部。

9. 发明申请

US20130002051A1 VOICE COIL MOTOR HOUSING AND VOICE COIL MOTOR USING SAME 失效
标题翻译：声音线圈电机外壳和声音线圈电机使用相同
公开(公告)号：US20130002051A1
公开(公告)日：2013-01-03
申请号：US13214262
申请日：2011-08-22
申请人： MAO-KUO HSU , MING-JU LEE
发明人： MAO-KUO HSU , MING-JU LEE
IPC分类号： H02K41/035 , H02K5/22
CPC分类号： H02K41/0356
摘要： A voice coil motor housing includes a top wall having an opening and four sidewalls extending from the top wall. The four sidewalls and the top wall cooperatively form a rectangular chamber opened at one end. Each of the sidewalls includes a top portion and a bottom portion. The top portions of the four sidewalls are connected to one another and forming a substantially gapless seam between each two adjacent sidewalls at the top portions. At least one slot is defined in the bottom portions of the sidewalls, the at least one slot is perpendicular to the top wall, and the slot is arranged adjacent to the corresponding gapless seam. At least one snap is arranged on the sidewalls at the corresponding bottom portion thereof, and the at least one snap protrudes inwardly of the chamber.
摘要翻译：音圈马达壳体包括具有开口的顶壁和从顶壁延伸的四个侧壁。四个侧壁和顶壁协同地形成在一端开口的矩形室。每个侧壁包括顶部和底部。四个侧壁的顶部彼此连接并且在顶部部分的每两个相邻侧壁之间形成基本上无间隙的接缝。至少一个狭槽限定在侧壁的底部中，至少一个狭槽垂直于顶壁，并且狭槽被布置成与相应的无间隙接缝相邻。至少一个卡扣布置在其对应底部的侧壁上，并且至少一个卡扣突出到该腔室的内部。

10. 发明申请

US20070104327A1 Error detection in high-speed asymmetric interfaces utilizing dedicated interface lines 有权
标题翻译：使用专用接口线路的高速非对称接口中的错误检测
公开(公告)号：US20070104327A1
公开(公告)日：2007-05-10
申请号：US11595619
申请日：2006-11-09
申请人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
发明人： Joseph Macri , Stephen Morein , Claude Gauthier , Ming-Ju Lee , Lin Chen
IPC分类号： H04N7/167
CPC分类号： H04L1/0045 , G06F11/08 , G06F11/10 , H04L1/0061 , H04L2001/0094
摘要： A system and method for detecting errors in high-speed asymmetric interfaces are described. Embodiments include transmitting digital data between a first system component and a second system component over a bidirectional interface, wherein the first component is significantly more intelligent than the second component. The first component receives a signature from the second component over a line of the interface concurrent with READ and WRITE operations over the interface. The latency associated with transmission of a signature from the second component to the first component is the time taken for the second component to compute a signature. The signature received is compared to a signature stored by the first component. Both signatures correspond to a particular READ or WRITE command. Based on the comparison, the first component determines whether the READ or WRITE operation was successful, and directs the second component as necessary.
摘要翻译：描述了用于检测高速非对称接口中的错误的系统和方法。实施例包括通过双向接口在第一系统组件和第二系统组件之间传输数字数据，其中第一组件比第二组件明显更智能。第一个组件通过接口的READ和WRITE操作同时从一个接口的一行接收第二个组件的签名。与从第二组件到第一组件的签名传输相关联的延迟是第二组件计算签名所花费的时间。所接收的签名与由第一组件存储的签名进行比较。两个签名对应于特定的READ或WRITE命令。基于比较，第一个组件确定READ或WRITE操作是否成功，并根据需要指示第二个组件。

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