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    • 4. 发明授权
    • Method and apparatus for testing a relatively slow speed component of an
intergrated circuit having mixed slow speed and high speed components
    • 用于测试具有混合的低速和高速分量的集成电路的相对较慢速度分量的方法和装置
    • US5870409A
    • 1999-02-09
    • US671011
    • 1996-06-28
    • Randy YachRodney Drake
    • Randy YachRodney Drake
    • G01R31/00G02F1/13G02F1/133G06F11/267G09G3/00G09G3/36H04N5/66G01R31/28
    • G09G3/006G06F11/2221
    • A method is disclosed for testing a high speed microcontroller fabricated on a semiconductor chip, and for testing relatively low speed functions of a liquid crystal display (LCD) module on the chip that drives an off-chip LCD for an external system to be controlled by the microcontroller with a plurality of discrete analog voltage levels for performing the LCD functions. Digital values are multiplexed in time slots of a test waveform to simulate in high speed digital format of a test mode the low speed timing, relative magnitude and functionality of analog voltage levels used to drive the LCD; A high speed driver is selectively coupled to a pin of the chip, to which the discrete analog voltage levels are normally applied at low speed to drive the LCD, and the test waveform is applied to the high speed driver. The digital values and timing that appear on the pin are then monitored as an indication of proper functionality of the LCD module. The high speed driver is switched out and the normal low speed LCD driver is switched back for return to an LCD user mode when the test mode is completed. Monitoring the pin with a digital tester allows verification that pin pulses in predetermined time slots indicate the corresponding analog voltage level is being applied at the proper time during normal operation of the LCD module, and digitally testing of continuity in an analog channel. A transistor normally employed on the chip for electrostatic discharge protection is activated to selectively couple the high speed driver to the pin for the high speed testing mode.
    • 公开了一种用于测试在半导体芯片上制造的高速微控制器的方法,并且用于测试芯片上的液晶显示器(LCD)模块的相对低速功能,该芯片驱动用于外部系统的片外LCD以由 具有用于执行LCD功能的多个离散模拟电压电平的微控制器。 数字值在测试波形的时隙中进行多路复用,以模拟用于驱动LCD的模拟电压电平的低速定时,相对幅度和功能的测试模式的高速数字格式; 选择性地将高速驱动器耦合到芯片的引脚,通过低速驱动分立的模拟电压电平来驱动LCD,测试波形被施加到高速驱动器。 然后监视引脚上出现的数字值和时序作为LCD模块正常功能的指示。 当测试模式完成时,高速驱动器被切换并且正常的低速LCD驱动器被切回以返回到LCD用户模式。 使用数字测试仪监控引脚,可以验证在预定时隙内的引脚脉冲表示在LCD模块正常工作期间的适当时间正在施加相应的模拟电压电平,并对模拟通道的连续性进行数字测试。 通常在芯片上用于静电放电保护的晶体管被​​激活以选择性地将高速驱动器耦合到用于高速测试模式的引脚。
    • 8. 发明申请
    • ESD structure having different thickness gate oxides
    • ESD结构具有不同厚度的栅极氧化物
    • US20070007597A1
    • 2007-01-11
    • US11215775
    • 2005-08-30
    • Randy YachPhilippe Deval
    • Randy YachPhilippe Deval
    • H01L23/62
    • H01L27/0266
    • An electrostatic discharge (ESD) structure having increased voltage withstand at an output terminal of an integrated circuit device has a thin gate oxide layer metal oxide semiconductor (MOS) device coupled in series with a thicker gate oxide layer MOS device. The thin gate oxide layer MOS device may be controlled by a low voltage control circuit of the integrated circuit. The thicker gate oxide layer MOS device may be coupled to an output of the integrated circuit device or a bipolar transistor may be coupled between the output of the integrated circuit device and the thicker gate oxide layer MOS device. The thin gate oxide layer and thicker gate oxide layer MOS devices may be coupled in series.
    • 在集成电路器件的输出端具有增加的耐压的静电放电(ESD)结构具有与较厚栅极氧化物层MOS器件串联耦合的薄栅极氧化物层金属氧化物半导体(MOS)器件。 薄栅氧化层MOS器件可以由集成电路的低压控制电路来控制。 较厚的栅极氧化物层MOS器件可以耦合到集成电路器件的输出,或者双极晶体管可以耦合在集成电路器件的输出和较厚栅极氧化物层MOS器件之间。 薄栅极氧化物层和较厚栅极氧化物层MOS器件可以串联耦合。
    • 9. 发明申请
    • LASER TARGET PRACTICE SYSTEM, METHOD AND APPARATUS
    • 激光瞄准实践系统,方法和装置
    • US20140134574A1
    • 2014-05-15
    • US14160840
    • 2014-01-22
    • Randy Yach
    • Randy YachPaul Katz
    • F41G3/26
    • F41G3/2655F41A33/02F41J5/00
    • Laser target practice using an ultra-violet light emitting laser that is pulsed on when a weapon trigger is pulled. The UV laser light pulse illuminates a spot on a target having a coating of phosphorescent material on a face thereof. The phosphorescent material within the illuminated spot glows for a certain time thereby visually indicating a location of the spot on the target. The UV laser light pulse may also illuminate a spot on a target having a photochromic paint coatings on a face thereof. The photochromic paint coatings within the illuminated spot changes color thereby indicating a location of the spot on the target.
    • 使用在武器扳机被拉动时脉冲的紫外光发射激光的激光瞄准练习。 紫外激光脉冲在其表面上照射具有磷光材料涂层的靶上的斑点。 照明光斑内的磷光材料发光一定时间,从而可视地显示光斑在靶上的位置。 UV激光脉冲也可以照射其表面上具有光致变色涂料的靶上的斑点。 照明区域内的光致变色涂料涂层改变颜色,从而指示目标点上的位置。
    • 10. 发明授权
    • Adaptive electrostatic discharge (ESD) protection of device interface for local interconnect network (LIN) bus and the like
    • 用于本地互联网络(LIN)总线的设备接口的自适应静电放电(ESD)保护等
    • US07885047B2
    • 2011-02-08
    • US12174903
    • 2008-07-17
    • Philippe DevalPatrick BesseuxRandy Yach
    • Philippe DevalPatrick BesseuxRandy Yach
    • H02H9/00
    • H01L27/0266H02H9/046
    • Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.
    • 器件接口的自适应静电放电(ESD)保护在处理或安装到系统或从系统中移除时具有非常好的ESD鲁棒性。 并且当其在系统中可操作时,具有对DPI,电磁干扰(EMI)等的强大的抗扰性。 在外部连接上没有(或低电平)DPI时,ESD保护金属氧化物半导体(MOS)器件的漏极和栅极之间存在显着的电容耦合,以增强ESD保护和较低的反冲电压。 。 因此当在外部连接上检测到显着的DPI / EMI信号时,MOS ESD保护器件的漏极和栅极之间的电容耦合被断开,旁路或衰减,从而增强了器件的DPI / EMI抗扰度。