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    • 1. 发明授权
    • Quotient remainder coverage system and method
    • 商品剩余覆盖系统和方法
    • US08040357B1
    • 2011-10-18
    • US11893418
    • 2007-08-15
    • Edward A. HutchinsChristopher D. S. Donham
    • Edward A. HutchinsChristopher D. S. Donham
    • G09G5/00
    • G06T11/40
    • Embodiments of the present invention pixel processing system and method provide convenient and efficient processing of pixel information. In one embodiment, quotient-remainder information associated with barycentric coordinate information indicating the location of a pixel is received. In one exemplary implementation quotient-remainder information is associated with barycentric coordinate information through the relationship c divided by dcdx, where c is the barycentric coordinate for a particular edge and dcdx is the derivative of the barycentric coordinate in the screen horizontal direction. The relationship of a pixel with respect to a primitive edge is determined based upon the quotient-remainder information. For example, a positive quotient can indicate a pixel is inside a triangle and a negative quotient can indicate a pixel is outside a triangle. Pixel processing such as shading is performed in accordance with the relationship of the pixel to the primitive.
    • 本发明的像素处理系统和方法的实施例提供了对像素信息的方便和有效的处理。 在一个实施例中,接收与指示像素的位置的重心坐标信息相关联的商剩余信息。 在一个示例性实施方案中,商余数信息通过除以dcdx的关系c与重心坐标信息相关联,其中c是特定边缘的重心坐标,dcdx是屏幕水平方向上的重心坐标的导数。 基于商余数信息确定像素与原始边缘的关系。 例如,正商可以指示像素在三角形内,而负商可以指示像素在三角形之外。 根据像素与原图的关系来执行诸如阴影的像素处理。
    • 2. 发明授权
    • Scoreboard cache coherence in a graphics pipeline
    • 记分板缓存在图形管道中的一致性
    • US09183607B1
    • 2015-11-10
    • US11893431
    • 2007-08-15
    • Justin M. MahanEdward A. HutchinsKevin P. AckenMichael J. M. ToksvigChristopher D. S. Donham
    • Justin M. MahanEdward A. HutchinsKevin P. AckenMichael J. M. ToksvigChristopher D. S. Donham
    • G06T1/20G06T1/00G06F15/00G06T15/00
    • G06T15/005G06T1/60G06T11/40
    • A method in system for latency buffered scoreboarding in a graphics pipeline of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality pixels related to the graphics primitive. An ID stored to account for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted to a subsequent stage of the graphics processor. A buffer is used to store the fragment data resulting from the parameter evaluation for each of the plurality of pixels by the subsequent stage. The ID and the fragment data from the buffering are compared to determine whether they correspond to one another. The completion of parameter evaluation for each of the plurality of pixels is accounted for when the ID and the fragment data match and as the fragment data is written to a memory.
    • 一种用于在图形处理器的图形管线中等待时间缓冲记分板的系统中的方法。 该方法包括在图形处理器的光栅级中接收用于光栅化的图形基元,并且对图形基元进行光栅化以生成与图形基元相关的多个像素。 存储的ID用于当像素被传送到图形处理器的后续阶段时考虑对于多个像素中的每一个的参数评估的启动。 缓冲器用于存储由后续阶段的多个像素中的每一个的参数评估产生的片段数据。 比较来自缓冲的ID和片段数据以确定它们是否彼此对应。 当ID和片段数据匹配并且片段数据被写入存储器时,对多个像素中的每一个的参数评估的完成进行了说明。
    • 7. 发明授权
    • Method and system for scalable, dataflow-based, programmable processing of graphics data
    • 用于可扩展,基于数据流,可编程处理图形数据的方法和系统
    • US06980209B1
    • 2005-12-27
    • US10172174
    • 2002-06-14
    • Christopher D. S. DonhamAlexander Lev MinkinBryon NordquistEdward A. HutchinsMark TianGeorge Easton Scott III
    • Christopher D. S. DonhamAlexander Lev MinkinBryon NordquistEdward A. HutchinsMark TianGeorge Easton Scott III
    • G06T15/00G06T15/50
    • G06T15/005
    • A scalable pipelined pixel shader that processes packets of data and preserves the format of each packet at each processing stage. Each packet is an ordered array of data values, at least one of which is an instruction pointer. Each member of the ordered array can be indicative of any type of data. As a packet progresses through the pixel shader during processing, each member of the ordered array can be replaced by a sequence of data values indicative of different types of data (e.g., an address of a texel, a texel, or a partially or fully processed color value). Information required for the pixel shader to process each packet is contained in the packet, and thus the pixel shader is scalable in the sense that it can be implemented in modular fashion to include any number of identical pipelined processing stages and can execute the same program regardless of the number of stages. Preferably, each processing stage is itself scalable, can be implemented to include an arbitrary number of identical pipelined instruction execution stages known as microblenders, and can execute the same program regardless of the number of microblenders. The current value of the instruction pointer (IP) in a packet determines the next instruction to be executed on the data contained in the packet. Any processing unit can change the instruction that will be executed by a subsequent processing unit by modifying the IP (and/or condition codes) of a packet that it asserts to the subsequent processing unit. Other aspects of the invention include graphics processors (each including a pixel shader configured in accordance with the invention), methods and systems for generating packets of data for processing in accordance with the invention, and methods for pipelined processing of packets of data.
    • 可扩展的流水线像素着色器,可处理数据包,并在每个处理阶段保留每个数据包的格式。 每个数据包是有序的数据值阵列,其中至少有一个是指令指针。 有序数组的每个成员可以指示任何类型的数据。 随着分组在处理期间通过像素着色器进行,有序阵列的每个成员可以被指示不同类型的数据的数据值序列(例如,纹素,纹素,或部分或完全处理的地址 颜色值)。 像素着色器处理每个数据包所需的信息包含在数据包中,因此像素着色器在可以以模块化方式实现以包括任意数量的相同流水线处理级并且可以执行相同的程序的意义上是可缩放的 的阶段数。 优选地,每个处理阶段本身是可扩展的,可以被实现为包括任意数量的称为微型混合器的相同的流水线指令执行阶段,并且可以执行相同的程序,而不管微型混合器的数量。 分组中的指令指针(IP)的当前值确定要对包含在分组中的数据执行的下一条指令。 任何处理单元可以通过修改后续处理单元确定的分组的IP(和/或条件代码)来改变将由后续处理单元执行的指令。 本发明的其他方面包括图形处理器(每个包括根据本发明配置的像素着色器),用于生成根据本发明进行处理的数据分组的方法和系统,以及用于流水线处理数据分组的方法。