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1. 发明授权

US09183607B1 Scoreboard cache coherence in a graphics pipeline 有权
标题翻译：记分板缓存在图形管道中的一致性
公开(公告)号：US09183607B1
公开(公告)日：2015-11-10
申请号：US11893431
申请日：2007-08-15
申请人： Justin M. Mahan , Edward A. Hutchins , Kevin P. Acken , Michael J. M. Toksvig , Christopher D. S. Donham
发明人： Justin M. Mahan , Edward A. Hutchins , Kevin P. Acken , Michael J. M. Toksvig , Christopher D. S. Donham
IPC分类号： G06T1/20 , G06T1/00 , G06F15/00 , G06T15/00
CPC分类号： G06T15/005 , G06T1/60 , G06T11/40
摘要： A method in system for latency buffered scoreboarding in a graphics pipeline of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality pixels related to the graphics primitive. An ID stored to account for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted to a subsequent stage of the graphics processor. A buffer is used to store the fragment data resulting from the parameter evaluation for each of the plurality of pixels by the subsequent stage. The ID and the fragment data from the buffering are compared to determine whether they correspond to one another. The completion of parameter evaluation for each of the plurality of pixels is accounted for when the ID and the fragment data match and as the fragment data is written to a memory.
摘要翻译：一种用于在图形处理器的图形管线中等待时间缓冲记分板的系统中的方法。该方法包括在图形处理器的光栅级中接收用于光栅化的图形基元，并且对图形基元进行光栅化以生成与图形基元相关的多个像素。存储的ID用于当像素被传送到图形处理器的后续阶段时考虑对于多个像素中的每一个的参数评估的启动。缓冲器用于存储由后续阶段的多个像素中的每一个的参数评估产生的片段数据。比较来自缓冲的ID和片段数据以确定它们是否彼此对应。当ID和片段数据匹配并且片段数据被写入存储器时，对多个像素中的每一个的参数评估的完成进行了说明。

2. 发明授权

US08004522B1 Using coverage information in computer graphics 有权
标题翻译：在计算机图形学中使用覆盖信息
公开(公告)号：US08004522B1
公开(公告)日：2011-08-23
申请号：US11890839
申请日：2007-08-07
申请人： Michael J. M. Toksvig , Brian K. Cabral , Edward A. Hutchins , Gary C. King , Christopher D. S. Donham
发明人： Michael J. M. Toksvig , Brian K. Cabral , Edward A. Hutchins , Gary C. King , Christopher D. S. Donham
IPC分类号： G06T15/50 , G09G5/00
CPC分类号： G06T15/503
摘要： The boundary of a surface can be represented as a series of line segments. A number of polygons are successively superimposed onto the surface. The polygons utilize a common reference point and each of the polygons has an edge that coincides with one of the line segments. Coverage bits are associated with respective sample locations within a pixel. A value of a coverage bit is changed each time a sample location associated with the coverage bit is covered by one of the polygons. Final values of the coverage bits are buffered after all of the polygons have been processed. The values of the coverage bits can be used when the surface is subsequently rendered.
摘要翻译：表面的边界可以表示为一系列线段。多个多边形依次叠加在表面上。多边形使用公共参考点，并且每个多边形具有与一个线段重合的边。覆盖位与像素内的相应样本位置相关联。每当与覆盖比特相关联的采样位置被多边形之一覆盖时，覆盖比特的值被改变。所有覆盖位的最终值在所有的多边形都被处理后被缓冲。当表面随后呈现时，可以使用覆盖位的值。

3. 发明授权

US07808512B1 Bounding region accumulation for graphics rendering 有权
标题翻译：图形渲染的边界区域积累
公开(公告)号：US07808512B1
公开(公告)日：2010-10-05
申请号：US11642276
申请日：2006-12-19
申请人： Edward A. Hutchins , Christopher D. S. Donham , Gary C. King , Michael J. M. Toksvig , Mark J. Kilgard
发明人： Edward A. Hutchins , Christopher D. S. Donham , Gary C. King , Michael J. M. Toksvig , Mark J. Kilgard
IPC分类号： G09G5/00
CPC分类号： G09G3/3611 , G09G5/225 , G09G2360/18
摘要： In a raster unit of a graphics processor, a method for bounding region accumulation for graphics rendering. The method includes receiving a plurality of graphics primitives for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitives to generate a plurality pixels related to the graphics primitives and a plurality of respective bounding regions related to the graphics primitives. Upon receiving an accumulation start command, the bounding regions are accumulated in an accumulation register. The accumulation continues until an accumulation stop command is received. The operation results in an accumulated bounding region. Access to the accumulated bounding region is enabled to facilitate a subsequent graphics rendering operation.
摘要翻译：在图形处理器的光栅单元中，用于界定图形渲染的区域累积的方法。该方法包括在图形处理器的光栅级中接收用于光栅化的多个图形基元，并且对图形基元进行光栅化以生成与图形基元相关的多个像素以及与图形基元相关的多个相应的边界区域。在接收到累加开始命令时，边界区域被累积在累加寄存器中。累积继续，直到接收到累加停止命令。操作会导致累积的边界区域。能够访问累积的边界区域以促进随后的图形绘制操作。

4. 发明授权

US07876332B1 Shader that conditionally updates a framebuffer in a computer graphics system 有权
标题翻译：着色器有条件地更新计算机图形系统中的帧缓冲区
公开(公告)号：US07876332B1
公开(公告)日：2011-01-25
申请号：US11643558
申请日：2006-12-20
申请人： Christopher D. S. Donham , Edward A. Hutchins , Gary C. King , Michael J. M. Toksvig
发明人： Christopher D. S. Donham , Edward A. Hutchins , Gary C. King , Michael J. M. Toksvig
IPC分类号： G09G5/00
CPC分类号： G09G5/393 , G06T11/40 , G06T15/005 , G09G5/363
摘要： A computer-implemented graphics system that includes a rasterizer and a shader has a mode of operation in which primitive coverage information is generated for real sample locations and virtual sample locations for use in anti-aliasing. An individual pixel includes a single real sample location and at least one virtual sample location. In some instances, a primitive may cover only virtual sample locations and does not cover a real sample location. These instances can be identified in the coverage information sent from the rasterizer to the shader, so that the shader can determine whether or not it can write color information, depth information and/or stencil information for the real sample location to a framebuffer.
摘要翻译：包括光栅化器和着色器的计算机实现的图形系统具有操作模式，其中为实际采样位置和用于抗锯齿的虚拟采样位置生成原始覆盖信息。单个像素包括单个实际采样位置和至少一个虚拟采样位置。在某些情况下，原语可能仅覆盖虚拟样本位置，并且不覆盖真实的样本位置。可以在从光栅化器发送到着色器的覆盖信息中识别这些实例，使得着色器可以确定它是否可以将真实样本位置的颜色信息，深度信息和/或模板信息写入帧缓冲器。

5. 发明授权

US08547395B1 Writing coverage information to a framebuffer in a computer graphics system 有权
标题翻译：将覆盖信息写入计算机图形系统中的帧缓冲区
公开(公告)号：US08547395B1
公开(公告)日：2013-10-01
申请号：US11643545
申请日：2006-12-20
申请人： Edward A. Hutchins , Christopher D. S. Donham , Gary C. King , Michael J. M. Toksvig
发明人： Edward A. Hutchins , Christopher D. S. Donham , Gary C. King , Michael J. M. Toksvig
IPC分类号： G09G5/00
CPC分类号： G06T15/005 , G06T11/40
摘要： A computer-implemented graphics system has a mode of operation in which primitive coverage information is generated by a rasterizer for real sample locations and virtual sample locations for use in anti-aliasing. An individual pixel includes a single real sample location and at least one virtual sample location. If the coverage information cannot be changed by a pixel shader, then the rasterizer can write the coverage information to a framebuffer. If, however, the coverage information can be changed by the shader, then the rasterizer sends the coverage information to the shader.
摘要翻译：计算机实现的图形系统具有操作模式，其中原始覆盖信息由光栅化器生成用于实际样本位置和用于抗锯齿的虚拟样本位置。单个像素包括单个实际采样位置和至少一个虚拟采样位置。如果覆盖信息不能被像素着色器改变，则光栅化器可以将覆盖信息写入帧缓冲区。然而，如果覆盖信息可以由着色器改变，则光栅化器将覆盖信息发送到着色器。

6. 发明授权

US07817165B1 Selecting real sample locations for ownership of virtual sample locations in a computer graphics system 有权
标题翻译：选择计算机图形系统中虚拟样本位置的所有权的实际样本位置
公开(公告)号：US07817165B1
公开(公告)日：2010-10-19
申请号：US11643185
申请日：2006-12-20
申请人： Christopher D. S. Donham , Edward A. Hutchins , Gary C. King , Michael J. M. Toksvig
发明人： Christopher D. S. Donham , Edward A. Hutchins , Gary C. King , Michael J. M. Toksvig
IPC分类号： G09G5/00
CPC分类号： G09G5/363 , G06T11/40 , G09G5/00 , G09G2340/10 , G09G2360/18
摘要： A computer-implemented graphics system has a mode of operation in which primitive coverage information is generated for real sample locations and virtual sample locations for use in anti-aliasing. An individual pixel includes a single real sample location and at least one virtual sample location. A block of real sample locations can be selected to delineate and encompass a region containing a number of virtual sample locations. Pixel attribute values (e.g., z-depth or stencil values) associated with the block of selected real sample locations can be used to associate each virtual sample location within the region with one of the selected real sample locations. The virtual sample location assumes the pixel attribute value of the real sample location with which it is associated.
摘要翻译：计算机实现的图形系统具有操作模式，其中为实际采样位置和用于抗锯齿的虚拟采样位置生成原始覆盖信息。单个像素包括单个实际采样位置和至少一个虚拟采样位置。可以选择实际样本位置的块来描绘并包含包含多个虚拟样本位置的区域。可以使用与所选择的实取样位置的块相关联的像素属性值（例如，z深度或模板值）将该区域内的每个虚拟样本位置与所选择的实际采样位置之一相关联。虚拟样本位置假定与其相关联的实际样本位置的像素属性值。

7. 发明授权

US08314803B2 Buffering deserialized pixel data in a graphics processor unit pipeline 有权
标题翻译：在图形处理器单元管道中缓冲反序列化像素数据
公开(公告)号：US08314803B2
公开(公告)日：2012-11-20
申请号：US11893499
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
IPC分类号： G06F15/80 , G06T1/20 , G09G5/36
CPC分类号： G06T1/20
摘要： An arithmetic logic stage in a graphics processor unit pipeline includes a number of arithmetic logic units (ALUs) and at least one buffer that stores pixel data for a group of pixels. Each clock cycle, the buffer stores one row of a series of rows of pixel data. A deserializer deserializes the rows of pixel data before the pixel data is placed in the buffer. After the buffer accumulates all rows of pixel data for a pixel, then the pixel data for the pixel can be operated on by the ALUs.
摘要翻译：图形处理器单元流水线中的算术逻辑级包括多个算术逻辑单元（ALU）和至少一个存储一组像素的像素数据的缓冲器。每个时钟周期，缓冲存储一行一系列像素数据。在将像素数据放置在缓冲器中之前，解串器反序列化像素数据行。在缓冲器累积像素的所有像素数据行之后，可以由ALU操作像素的像素数据。

8. 发明授权

US08856499B1 Reducing instruction execution passes of data groups through a data operation unit 有权
标题翻译：通过数据操作单元减少数据组的指令执行次数
公开(公告)号：US08856499B1
公开(公告)日：2014-10-07
申请号：US11893615
申请日：2007-08-15
申请人： Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins , Tyson J. Bergland , James T. Battle , Ashok Srinivasan
发明人： Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins , Tyson J. Bergland , James T. Battle , Ashok Srinivasan
IPC分类号： G06F15/00 , G06F7/38 , G06F9/44 , G06F9/00
CPC分类号： G06F9/3836 , G06F9/321 , G06F9/381 , G06F9/383
摘要： An apparatus is disclosed. The apparatus comprises an instruction mapping table, which includes a plurality of instruction counts and a plurality of instruction pointers each corresponding with one of the instruction counts. Each instruction pointer identifies a next instruction for execution. Further, each instruction count specifies a number of instructions to execute beginning with the next instruction. The apparatus also has a data operation unit adapted to receive a data group and adapted to execute on the received data group the number of instructions specified by a current instruction count of the instruction mapping table beginning with the next instruction identified by a current instruction pointer of the instruction mapping table before proceeding with another data group.
摘要翻译：公开了一种装置。该装置包括指令映射表，其包括多个指令计数和多个指令指针，每个指令指针与指令计数之一相对应。每个指令指针标识下一个执行指令。此外，每个指令计数指定从下一条指令开始执行的指令数。该装置还具有数据操作单元，该数据操作单元适于接收数据组并适于在接收到的数据组上执行指令映射表的当前指令计数指定的指令数，该指令开始于由当前指令指针在进行另一个数据组之前的指令映射表。

9. 发明授权

US08599208B2 Shared readable and writeable global values in a graphics processor unit pipeline 有权
公开(公告)号：US08599208B2
公开(公告)日：2013-12-03
申请号：US11893622
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
发明人： Tyson J. Bergland , Craig M. Okruhlica , Edward A. Hutchins , Michael J. M. Toksvig , Justin M. Mahan
IPC分类号： G06F12/02 , G06F15/80 , G09G5/36
CPC分类号： G09G5/363 , G06F9/30098 , G06F9/3879 , G06T1/20 , G06T15/005
摘要： An arithmetic logic stage in a graphics processor unit includes arithmetic logic units (ALUs) and global registers. The registers contain global values for a group of pixels. Global values may be read from any of the registers, regardless of which of the pixels is being operated on by the ALUs. However, when writing results of the ALU operations, only some of the global registers are candidates to be written to, depending on the pixel number. Accordingly, overwriting of data is prevented.

10. 发明授权

US08775777B2 Techniques for sourcing immediate values from a VLIW 有权
标题翻译：从VLIW采购即时价值的技术
公开(公告)号：US08775777B2
公开(公告)日：2014-07-08
申请号：US11893584
申请日：2007-08-15
申请人： Tyson J. Bergland , Craig M. Okruhlica , Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins
发明人： Tyson J. Bergland , Craig M. Okruhlica , Michael J. M. Toksvig , Justin M. Mahan , Edward A. Hutchins
IPC分类号： G06F15/76
CPC分类号： G06F9/3016 , G06F9/30036 , G06F9/30167 , G06F9/30185 , G06F9/3853 , G06F9/3885 , G06T15/005
摘要： Sourcing immediate values from a very long instruction word includes determining if a VLIW sub-instruction expansion condition exists. If the sub-instruction expansion condition exists, operation of a portion of a first arithmetic logic unit component is minimized. In addition, a part of a second arithmetic logic unit component is expanded by utilizing a block of a very long instruction word, which is normally utilized by the first arithmetic logic unit component, for the second arithmetic logic unit component if the sub-instruction expansion condition exists.
摘要翻译：从非常长的指令字中采集即时值包括确定是否存在VLIW子指令扩展条件。如果存在子指令扩展条件，则将第一算术逻辑单元组件的一部分的操作最小化。此外，如果副指令扩展，则第二算术逻辑单元组件的一部分通过利用第二算术逻辑单元组件通常由第一算术逻辑单元组件使用的非常长的指令字的块来扩展条件存在。

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