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1. 发明授权

US5793083A Method for designing shallow junction, salicided NMOS transistors with decreased electrostatic discharge sensitivity 失效
标题翻译：用于设计具有降低的静电放电灵敏度的浅结，水银NMOS晶体管的方法
公开(公告)号：US5793083A
公开(公告)日：1998-08-11
申请号：US755924
申请日：1996-11-25
申请人： E. Ajith Amerasekera , Vincent M. McNeil , Mark S. Rodder
发明人： E. Ajith Amerasekera , Vincent M. McNeil , Mark S. Rodder
IPC分类号： H01L29/78 , H01L27/02 , H01L29/08 , H01L29/45 , H01L29/739 , H01L23/62
CPC分类号： H01L27/0266 , H01L29/0847 , H01L29/7393 , H01L29/456
摘要： A technique for providing a design window for scaled technologies in which good electrostatic discharge/electrical over stress damage and optimum transistor operation can be achieved without the use of additional masks or design steps. The M, beta, and R.sub.sub parameters of the NMOS transistor 13 and associated parasitic npn transistor 10 are selected to provide the design window.
摘要翻译：提供一种用于缩放技术的设计窗口的技术，其中可以在不使用附加掩模或设计步骤的情况下实现良好的静电放电/电过应力损坏和最佳晶体管操作。选择NMOS晶体管13和相关联的寄生npn晶体管10的M，β和Rsub参数以提供设计窗口。

2. 发明授权

US6040968A EOS/ESD protection for high density integrated circuits 失效
标题翻译：高密度集成电路的EOS / ESD保护
公开(公告)号：US6040968A
公开(公告)日：2000-03-21
申请号：US99654
申请日：1998-06-17
申请人： Charvaka Duvvury , E. Ajith Amerasekera , Sridhar Ramaswamy
发明人： Charvaka Duvvury , E. Ajith Amerasekera , Sridhar Ramaswamy
IPC分类号： H01L27/02 , H02H9/00
CPC分类号： H01L27/0251 , H01L27/0248
摘要： A method for achieving improving ESD protection in integrated circuits. Capacitance associated with a power supply plays an important role in ESD protection and increasing Vcc.sub.-- c capacitance by integrating distributed capacitors as junction capacitors, or MOS capacitors along Vcc and grounded n+ diffusion parallel runs improves protection against ESD and EOS. Additionally, at least a pair of antiparallel diodes interposed between the periphery voltage source and internal core circuitry voltage provides an added noise margin.
摘要翻译：实现集成电路中ESD保护改进的方法。与电源相关的电容在ESD保护中起着重要作用，通过将分布式电容器集成为结电容器，或沿着Vcc和接地的n +扩散并联运行的MOS电容器提高Vcc-c电容，提高了ESD和EOS的保护。此外，插入在外围电压源和内部电路电压之间的至少一对反并联二极管提供了增加的噪声容限。

3. 发明授权

US6137144A On-chip ESD protection in dual voltage CMOS 有权
标题翻译：双电压CMOS中的片上ESD保护
公开(公告)号：US6137144A
公开(公告)日：2000-10-24
申请号：US281189
申请日：1999-03-30
申请人： Alwin J. Tsao , Vikas I. Gupta , Gregory C. Baldwin , E. Ajith Amerasekera , David B. Spratt , Timothy A. Rost
发明人： Alwin J. Tsao , Vikas I. Gupta , Gregory C. Baldwin , E. Ajith Amerasekera , David B. Spratt , Timothy A. Rost
IPC分类号： H01L27/02 , H01L23/62
CPC分类号： H01L27/0262 , H01L27/0266
摘要： In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.
摘要翻译：在双电压芯片的分离栅极工艺中，作为ESD保护电路的一部分，因此具有较高栅极氧化物的高压晶体管的N型高压晶体管可以接收沟道掺杂和漏极延长器掺杂，与芯晶体管相同。这导致这些晶体管在ESD事件期间产生高衬底电流，从而触发保护电路。

4. 发明授权

US5949094A ESD protection for high density DRAMs using triple-well technology 失效
标题翻译：使用三重阱技术的高密度DRAM的ESD保护
公开(公告)号：US5949094A
公开(公告)日：1999-09-07
申请号：US920998
申请日：1997-08-29
申请人： E. Ajith Amerasekera
发明人： E. Ajith Amerasekera
IPC分类号： H01L27/02 , H01L29/74 , H01L29/76 , H01L29/94 , H01L31/111
CPC分类号： H01L27/0262
摘要： An ESD protected semiconductor circuit and the ESD protection circuit. The protected circuit includes a terminal, a semiconductor device coupled to the terminal and an ESD protection circuit. The ESD protection circuit includes a substrate of a first conductivity type and has a surface. A first well of conductivity type opposite to the first conductivity type is disposed within the substrate and extends to the surface. A second well of the first conductivity type is disposed within the first well and is spaced from the substrate and extending to the surface. A third region of the opposite conductivity type is disposed within the second well and is spaced from the first well and extending to the surface. At least one of the substrate or the third region is coupled to the terminal.
摘要翻译： ESD保护半导体电路和ESD保护电路。保护电路包括端子，耦合到端子的半导体器件和ESD保护电路。 ESD保护电路包括第一导电类型的衬底并具有表面。导电类型与第一导电类型相反的第一阱设置在衬底内并延伸到表面。第一导电类型的第二阱设置在第一阱内并且与衬底间隔开并延伸到表面。相反导电类型的第三区域设置在第二阱内并且与第一阱间隔开并延伸到表面。衬底或第三区域中的至少一个耦合到端子。

5. 发明授权

US06628493B1 System and method for electrostatic discharge protection using lateral PNP or PMOS or both for substrate biasing 有权
标题翻译：使用横向PNP或PMOS或两者用于衬底偏置的静电放电保护的系统和方法
公开(公告)号：US06628493B1
公开(公告)日：2003-09-30
申请号：US09546988
申请日：2000-04-11
申请人： Zhiliang Julian Chen , Thomas A. Vrotsos , E. Ajith Amerasekera
发明人： Zhiliang Julian Chen , Thomas A. Vrotsos , E. Ajith Amerasekera
IPC分类号： H02H900
CPC分类号： H01L27/027 , H01L27/0259 , H01L2924/0002 , H01L2924/00
摘要： The invention comprises a system and method for providing electrostatic discharge protection. In one embodiment of the invention, an integrated circuit (10) comprising at least one input element (20) is protected by a protective circuit (40). The protective circuit (40) is operable to protect the integrated circuit (10) from damage due to electrostatic discharge and may be coupled to the input element (20). The protective circuit (40) comprises a lateral NPN transistor (T1) coupled to the input element (20) and operable to activate when the input element voltage exceeds threshold, the threshold greater than or equal to the ordinary operating voltage of circuitry coupled to the input element (20). The protective circuit (40) also may comprise a lateral PNP transistor (T2) coupled to the input element (20) and to the lateral NPN transistor (T1). The lateral PNP transistor (T2) is operable to aid in raising a potential of the base of the lateral NPN transistor (T1). Alternatively, the protective circuit (40) also may use a PMOS traisistor (P1), or a PMOS transistor (P1) in combination with the lateral NPN transistor (T1), coupled to the input element (20) and to the lateral NPN transistor (T1). The PMOS transistor (P1) is operable to aid in raising the potential of the base of the lateral NPN transistor (T1).
摘要翻译：本发明包括提供静电放电保护的系统和方法。在本发明的一个实施例中，包括至少一个输入元件（20）的集成电路（10）由保护电路（40）保护。保护电路（40）可操作以保护集成电路（10）免受静电放电所造成的损坏，并可与输入元件（20）耦合。保护电路（40）包括耦合到输入元件（20）的横向NPN晶体管（T1），并且可操作以在输入元件电压超过阈值时启动，阈值大于或等于耦合到该电路的电路的正常工作电压输入元件（20）。保护电路（40）还可以包括耦合到输入元件（20）和横向NPN晶体管（T1）的横向PNP晶体管（T2）。横向PNP晶体管（T2）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。或者，保护电路（40）还可以使用与横向NPN晶体管（T1）组合的PMOS晶体管（P1）或PMOS晶体管（P1），耦合到输入元件（20）和横向NPN晶体管（T1）。 PMOS晶体管（P1）可操作以帮助提高横向NPN晶体管（T1）的基极的电位。

6. 发明授权

US06433392B1 Electrostatic discharge device and method 有权
标题翻译：静电放电装置及方法
公开(公告)号：US06433392B1
公开(公告)日：2002-08-13
申请号：US09456036
申请日：1999-12-03
申请人： E. Ajith Amerasekera , Vikas Gupta , Stanton P. Ashburn
发明人： E. Ajith Amerasekera , Vikas Gupta , Stanton P. Ashburn
IPC分类号： H01L2362
CPC分类号： H01L27/0262 , H01L27/0266 , H01L29/87
摘要： The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.
摘要翻译：用于作为防止由于静电放电（ESD）事件引起的劣化的保护装置的横向npn晶体管的高电流能力通过调节集电极电流从雪崩pn结流到晶片的材料的电阻率来改进背面接触。如以第二阈值表示，报告了改进系数为4的因素。描述了两种植入序列，其应用局部掩蔽和标准植入条件以实现改进，而不增加工艺步骤的总数。 p阱工程原理扩展到采用SCR型器件的ESD保护器件。

7. 发明授权

US06530064B1 Method and apparatus for predicting an operational lifetime of a transistor 失效
标题翻译：用于预测晶体管的工作寿命的方法和装置
公开(公告)号：US06530064B1
公开(公告)日：2003-03-04
申请号：US09692692
申请日：2000-10-19
申请人： Karthik Vasanth , Shian-Wei Aur , E. Ajith Amerasekera , Sharad Saxena , Joseph C. Davis , Richard G. Burch
发明人： Karthik Vasanth , Shian-Wei Aur , E. Ajith Amerasekera , Sharad Saxena , Joseph C. Davis , Richard G. Burch
IPC分类号： G06F1750
CPC分类号： G06F17/5036 , G06F17/18
摘要： An operational lifetime, and also performance characteristics, can be accurately predicted for an experimental transistor design (10) and a specified set of fabrication process conditions (117), without actually fabricating and testing a physical transistor made according to the particular design data and process conditions. With respect to the prediction of an operational lifetime, the operational lifetime can be expressed as a function of the size of a gate overlap (12) of the transistor, and this relationship is valid throughout a selected semiconductor technology for which the transistor is designed. The size of the gate overlap is determined by selecting a combinations of values for two process conditions.
摘要翻译：无需实际制造和测试根据特定设计数据和过程制造的物理晶体管，可以准确预测实验晶体管设计（10）和指定的制造工艺条件（117）集合的运行寿命和性能特性条件。关于工作寿命的预测，可以将工作寿命表示为晶体管的栅极重叠（12）的大小的函数，并且该关系在设计晶体管的所选择的半导体技术中是有效的。通过选择两个处理条件的值的组合来确定栅极重叠的大小。

8. 发明授权

US06469353B1 Integrated ESD protection circuit using a substrate triggered lateral NPN 失效
标题翻译：集成ESD保护电路采用基板触发横向NPN
公开(公告)号：US06469353B1
公开(公告)日：2002-10-22
申请号：US08673939
申请日：1996-07-01
申请人： E. Ajith Amerasekera , Charvaka Duvvury
发明人： E. Ajith Amerasekera , Charvaka Duvvury
IPC分类号： H01L2362
CPC分类号： H01L27/0259
摘要： An ESD protection circuit (100) and method is described herein. A lateral npn transistor (104) is connected between an I/O pad (110) and ground (GND). A substrate biasing circuit (150) increases the voltage across a substrate resistance (114) during an ESD event by conducting current through the substrate. This, in turn, triggers the lateral npn (104) which clamps to voltage at the pad (110) and dissipated the ESD current. The lateral npn (104) is the primary protection device for dissipating ESD current.
摘要翻译：本文描述了ESD保护电路（100）和方法。横向npn晶体管（104）连接在I / O焊盘（110）和地（GND）之间。衬底偏置电路（150）通过传导电流通过衬底来增加ESD事件期间衬底电阻（114）上的电压。这反过来触发钳位在焊盘（110）处的电压的横向npn（104）并消耗ESD电流。横向npn（104）是消除ESD电流的主要保护装置。

9. 发明授权

US6143594A On-chip ESD protection in dual voltage CMOS 有权
公开(公告)号：US6143594A
公开(公告)日：2000-11-07
申请号：US491604
申请日：2000-01-26
申请人： Alwin J. Tsao , Vikas I. Gupta , Gregory C. Baldwin , E. Ajith Amerasekera , David B. Spratt , Timothy A. Rost
发明人： Alwin J. Tsao , Vikas I. Gupta , Gregory C. Baldwin , E. Ajith Amerasekera , David B. Spratt , Timothy A. Rost
IPC分类号： H01L27/02 , H01L21/8238
CPC分类号： H01L27/0262 , H01L27/0266
摘要： In a split gate process for dual voltage chips, the N-type high-voltage transistors which are part of the ESD protection circuit, and therefore have the thicker gate oxide of the high-voltage transistors, can receive channel doping and drain extender doping which is the same as the core transistors. This causes these transistors to develop a high substrate current during an ESD event, triggering the protection circuit.

10. 发明授权

US07456477B2 Electrostatic discharge device and method 有权
标题翻译：静电放电装置及方法
公开(公告)号：US07456477B2
公开(公告)日：2008-11-25
申请号：US10191902
申请日：2002-07-09
申请人： E. Ajith Amerasekera , Vikas Gupta , Stanton P. Ashburn
发明人： E. Ajith Amerasekera , Vikas Gupta , Stanton P. Ashburn
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L27/0266 , H01L29/87
摘要： The high current capabilities of a lateral npn transistor for application as a protection device against degradation due to electrostatic discharge (ESD) events are improved by adjusting the electrical resistivity of the material through which the collector current flows from the avalanching pn-junction to the wafer backside contact. As expressed in terms of the second threshold current improvements by a factor of 4 are reported. Two implant sequences are described which apply local masking and standard implant conditions to achieve the improvements without adding to the total number of process steps. The principle of p-well engineering is extended to ESD protection devices employing SCR-type devices.
摘要翻译：用于作为防止由于静电放电（ESD）事件引起的劣化的保护装置的横向npn晶体管的高电流能力通过调节集电极电流从雪崩pn结流到晶片的材料的电阻率来改进背面接触。如以第二阈值表示，报告了改进系数为4的因素。描述了两种植入序列，其应用局部掩蔽和标准植入条件以实现改进，而不增加工艺步骤的总数。 p阱工程原理扩展到采用SCR型器件的ESD保护器件。

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