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    • 1. 发明授权
    • Fabrication of gated electron-emitting devices utilizing distributed particles to define gate openings, typically in combination with lift-off of excess emitter material
    • 使用分布式颗粒来限定栅极开口的门控电子发射器件的制造,通常结合多余的发射极材料的剥离
    • US06187603B1
    • 2001-02-13
    • US08660536
    • 1996-06-07
    • Duane A. HavenN. Johan KnallPaul N. LudwigJohn M. Macaulay
    • Duane A. HavenN. Johan KnallPaul N. LudwigJohn M. Macaulay
    • H01L2100
    • H01J9/025H01J2329/00
    • An electron-emitting device is fabricated by a process in which particles (46) are distributed over an initial structure. The particles are utilized in defining primary openings (52, 64, or 78) that extend through a primary layer (50A, 62A, or 72) provided over a gate layer (48A, 60A, or 60B) formed over an insulating layer (44) and in defining corresponding gate openings (54, 66, or 80) that extend through the gate layer. The insulating layer is etched through the primary and gate openings to form corresponding dielectric openings (56 or 68) through the insulating layer down to a lower non-insulating region (42). Electron-emissive elements (58A or 70A) are formed over the lower non-insulating region so that each electron-emissive element is at least partially situated in one dielectric opening. Formation of the electron-emissive elements, typically in the shape of cones, normally entails depositing emitter material over the primary layer, through the primary and gate openings, and into the dielectric openings and then removing the primary layer so as to remove any emitter material accumulated over the primary layer.
    • 通过其中颗粒(46)分布在初始结构上的过程制造电子发射器件。 这些颗粒用于限定主开口(52,64或78),其延伸穿过形成在绝缘层(44)上的栅极层(48A,60A或60B)上的初级层(50A,62A或72) )并且限定延伸穿过栅极层的对应的栅极开口(54,66或80)。 通过初级和栅极开口蚀刻绝缘层,以形成穿过绝缘层的相应电介质开口(56或68),直到下部非绝缘区域(42)。 电子发射元件(58A或70A)形成在下部非绝缘区域上,使得每个电子发射元件至少部分地位于一个电介质开口中。 电子发射元件的形成(通常为锥形)通常需要在初级层上通过初级和栅极开口沉积发射极材料,并将其沉积到电介质开口中,然后去除主层以除去任何发射体材料 累积在主层上。
    • 5. 发明授权
    • Multi-step removal of excess emitter material in fabricating
electron-emitting device
    • 在制造电子发射器件时多步去除过量的发射极材料
    • US6027632A
    • 2000-02-22
    • US904967
    • 1997-07-30
    • N. Johan KnallDuane A. HavenRoger W. BartonWilliam H. CreelChristopher J. Spindt
    • N. Johan KnallDuane A. HavenRoger W. BartonWilliam H. CreelChristopher J. Spindt
    • B81C1/00C25F3/14H01J9/02C25F3/02
    • H01J9/025
    • Excess emitter material (52B) is removed in multiple steps during the fabrication of an electron-emitting device. A structure is initially provided in which a dielectric layer (44) overlies a non-insulating region (42), control electrodes (80 or 46/80) overlie the dielectric layer, openings (48/50) extend through the control electrodes and dielectric layer, electron-emissive elements (52A) formed with emitter material are situated in the openings, and an excess layer (52B) of the emitter material overlies the control electrodes and the dielectric layer. Portions of the excess emitter material overlying the dielectric layer in the spaces between the control electrodes are initially removed, preferably with etchant that directly attacks the emitter material. Portions (52C) of the excess emitter material overlying the control electrodes above the electron-emissive elements are subsequently removed to expose the electron-emissive elements.
    • 在制造电子发射器件期间,多个发射极材料(52B)被多个步骤去除。 首先提供一种结构,其中介电层(44)覆盖在非绝缘区域(42)上,控制电极(80或46/80)覆盖在电介质层上,开口(48/50)延伸穿过控制电极和电介质 由发射体材料形成的层,电子发射元件(52A)位于开口中,发射极材料的过剩层(52B)覆盖在控制电极和电介质层上。 最初除去在控制电极之间的空间中覆盖电介质层的多余发射体材料的部分,最好用直接攻击发射极材料的蚀刻剂。 随后去除覆盖电子发射元件上方的控制电极的过量发射体材料的部分(52℃)以露出电子发射元件。
    • 9. 发明授权
    • Electrically isolated pillars in active devices
    • 有源器件中电隔离柱
    • US07245000B2
    • 2007-07-17
    • US10681504
    • 2003-10-07
    • Michael A. VyvodaManish BhatiaJames M. CleevesN. Johan Knall
    • Michael A. VyvodaManish BhatiaJames M. CleevesN. Johan Knall
    • H01L27/103
    • H01L27/1021
    • A monolithic three dimensional memory array is described. The memory array comprises a first set of strips including a first terminal; a second set of strips including a second terminal; a third set of strips including a third terminal; a first pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said first and second sets of strips, and including a first P doped silicon region, a first N doped silicon region and a first insulating region; a second pillar having at least one side wall with a slightly positive slope, said pillar disposed between and connecting said second and third sets of strips, and including a second P doped silicon region, a second N doped silicon region and a second insulating region; wherein each of the pillars is substantially free of stringers.
    • 描述了单片三维存储器阵列。 存储器阵列包括第一组条带,包括第一端子; 第二组条带,包括第二端子; 第三组条带,包括第三端子; 具有至少一个具有稍微正斜率的侧壁的第一柱,所述柱设置在所述第一和第二组条之间并连接所述第一和第二组条,并且包括第一P掺杂硅区,第一N掺杂硅区和第一绝缘区; 具有至少一个具有稍微正斜率的侧壁的第二柱,所述柱设置在所述第二和第三组条之间并连接所述第二和第三组条,并包括第二P掺杂硅区,第二N掺杂硅区和第二绝缘区; 其中每个支柱基本上没有桁条。
    • 10. 发明授权
    • Apparatus and method for disturb-free programming of passive element memory cells
    • 无源元件存储单元无干扰编程的装置和方法
    • US06822903B2
    • 2004-11-23
    • US10403488
    • 2003-03-31
    • Roy E. ScheuerleinN. Johan Knall
    • Roy E. ScheuerleinN. Johan Knall
    • G11C1134
    • G11C13/0014B82Y10/00G11C17/16G11C17/165G11C2213/71G11C2213/72
    • In a passive element memory array, such as a rail stack array having a continuous semiconductor region along one or both of the array lines, programming a memory cell may disturb nearby memory cells as result of a leakage path along the array line from the selected cell to the adjacent cell. This effect may be reduced substantially by changing the relative timing of the programming pulses applied to the array lines for the selected memory cell, even if the voltages are unchanged. In an exemplary three-dimensional antifuse memory array, a positive-going programming pulse applied to the anode region of the memory cell preferably is timed to lie within the time that a more lightly-doped cathode region is pulsed low.
    • 在无源元件存储器阵列中,例如沿着阵列线中的一个或两个具有连续半导体区域的轨道堆叠阵列,对存储器单元的编程可能由于沿着阵列线从所选择的单元的泄漏路径而扰乱附近的存储器单元 到相邻的单元格。 即使电压不变,也可以通过改变施加到所选择的存储单元的阵列线的编程脉冲的相对定时来大大减小该效果。 在示例性三维反熔丝存储器阵列中,施加到存储单元的阳极区域的正向编程脉冲优选地被定时在更轻掺杂的阴极区域被脉冲为低的时间内。