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1. 发明授权

US07518189B1 Independently-double-gated field effect transistor 有权
标题翻译：独立双门控场效应晶体管
公开(公告)号：US07518189B1
公开(公告)日：2009-04-14
申请号：US11307863
申请日：2006-02-25
申请人： Douglas R. Hackler, Sr. , Stephen A. Parke
发明人： Douglas R. Hackler, Sr. , Stephen A. Parke
IPC分类号： H01L29/94
CPC分类号： H01L21/2256 , H01L21/823437 , H01L21/84 , H01L27/088 , H01L27/098 , H01L27/1203 , H01L29/4908 , H01L29/66484 , H01L29/66553 , H01L29/66583 , H01L29/66772 , H01L29/7832 , H01L29/78621 , H01L29/78648 , H01L29/8086 , H01L29/8124 , H03K19/0948
摘要： This independent double-gated transistor architecture creates a MOSFET, JFET or MESFET in parallel with a JFET. Its two gates may be configured to provide a four-terminal device for independent gate control, a floating gate device, and a double-gate device. First and second insulating spacers are disposed on opposing sides of the top gate with the first spacer between the source and the top gate and the second spacer between the drain and the top gate. Source and drain extensions extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain and further resist compression of the channel by the source and drain. Truly independent control of the two gates makes possible many 2-, 3- and 4-terminal device configurations that may be dynamically reconfigured to trade off speed against power. The resulting transistors exhibit inherent radiation tolerance.
摘要翻译：这种独立的双门控晶体管架构与JFET并联产生MOSFET，JFET或MESFET。其两个门可以被配置为提供用于独立门控制的四端子器件，浮动栅极器件和双栅极器件。第一和第二绝缘间隔物设置在顶部栅极的相对侧上，第一间隔物在源极和顶部栅极之间，第二间隔物位于漏极和顶部栅极之间。源极和漏极延伸部分靠近间隔件延伸并耦合到通道。间隔物屏蔽通道与源极和漏极的场效应，并进一步抵抗通过源极和漏极压缩沟道。对两个门的真正的独立控制使得许多可以被动态重新配置的两个，三个和四个终端设备配置成为能够抵消电力的速度。所得的晶体管表现出固有的辐射耐受性。

2. 发明授权

US07019342B2 Double-gated transistor circuit 有权
标题翻译：双门控晶体管电路
公开(公告)号：US07019342B2
公开(公告)日：2006-03-28
申请号：US10719119
申请日：2003-11-21
申请人： Douglas R. Hackler, Sr. , Stephen A. Parke
发明人： Douglas R. Hackler, Sr. , Stephen A. Parke
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H01L29/7832 , H01L21/2256 , H01L21/823437 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/66553 , H01L29/66583 , H01L29/66772 , H01L29/78648 , H03K19/0948
摘要： An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.
摘要翻译： OR门电路包括具有独立门控制的双门控四端子晶体管。第一和第二输入独立地耦合到晶体管的顶部和底部栅极。漏极耦合到输出并预充电到低电压。输入到顶部或底部栅极导致漏极的高电压，输出值为1。

3. 发明授权

US06919647B2 SRAM cell 有权
标题翻译： SRAM单元
公开(公告)号：US06919647B2
公开(公告)日：2005-07-19
申请号：US10733612
申请日：2003-12-11
申请人： Douglas R. Hackler, Sr. , Stephen A. Parke , Kelly James Degregorio
发明人： Douglas R. Hackler, Sr. , Stephen A. Parke , Kelly James Degregorio
IPC分类号： H01L21/225 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/12 , H01L29/786 , H03K19/0948 , H01L27/11
CPC分类号： H01L21/2256 , H01L21/823437 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/66553 , H01L29/66583 , H01L29/66772 , H01L29/7832 , H01L29/78648 , H03K19/0948 , Y10S257/903
摘要： A SRAM cell includes double-gated PMOS and NMOS transistors to form a latch and retain a value. The unique MOSFET transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate, and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain, and further resist compression of the channel by the source and drain.
摘要翻译： SRAM单元包括双门控PMOS和NMOS晶体管，以形成锁存器并保持一个值。独特的MOSFET晶体管架构提供了一个用于独立门控制的四端子器件，一个浮体器件和一个动态阈值器件。通道可以具有U形横截面积以增加通道长度和门控制。第一和第二绝缘间隔物设置在顶部栅极的相对侧上，使得第一间隔物在源极和顶部栅极之间，并且第二间隔物位于漏极和顶部栅极之间。源极和漏极包括靠近间隔物延伸并连接到沟道的延伸部分。间隔件将通道与源极和漏极的场效应隔离，并进一步抵抗通过源极和漏极的通道的压缩。

4. 发明授权

US08072006B1 Double-gated sensor cell 有权
标题翻译：双门传感器单元
公开(公告)号：US08072006B1
公开(公告)日：2011-12-06
申请号：US11306292
申请日：2005-12-21
申请人： Douglas R. Hackler, Sr. , Richard A. Hayhurst , Stephen A. Parke
发明人： Douglas R. Hackler, Sr. , Richard A. Hayhurst , Stephen A. Parke
IPC分类号： H01L29/76
CPC分类号： H01L27/14689
摘要： A high quality imager is constructed using a silicon-on-insulator (SOI) process with sensors fabricated in the SOI substrate and isolated by the buried oxide (BOX) from associated readout circuitry in the SOI layer. Handle windows are opened in the SOI device layer for fabrication of the sensors in the handle layer substrate and then closed prior to processing in the device layer. By keeping the buried oxide layer intact, the described technique allows for independent processing of sensors and readout circuitry so that each is optimized with regard to thermal and dopant properties without concern for degradation of the other. The process is compatible with the fabrication of readout circuitry using transistors having independent double-gates, which offer simultaneous advantages in scalability, low power and low noise. Photodiode sensors are shown with allowance for many other types of sensors. The process easily accommodates hardening against radiation.
摘要翻译：使用在SOI衬底中制造的传感器并通过SOI层中的相关读出电路的掩埋氧化物（BOX）隔离的传感器来构建使用绝缘体上硅（SOI）工艺的高质量成像器。处理窗在SOI器件层中打开，用于制造处理层衬底中的传感器，然后在器件层中处理之前封闭。通过保持掩埋氧化物层的完整性，所描述的技术允许传感器和读出电路的独立处理，使得每个都相对于热和掺杂剂性质而优化，而不考虑另一个的劣化。该过程与使用具有独立双栅极的晶体管的读出电路的制造兼容，其提供可扩展性，低功率和低噪声的同时优势。显示光电二极管传感器，允许许多其他类型的传感器。该过程容易适应辐射硬化。

5. 发明授权

US07154135B2 Double-gated transistor circuit 有权
公开(公告)号：US07154135B2
公开(公告)日：2006-12-26
申请号：US11273362
申请日：2005-11-14
申请人： Douglas R. Hackler, Sr. , Stephen A. Parke
发明人： Douglas R. Hackler, Sr. , Stephen A. Parke
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H01L29/7832 , H01L21/2256 , H01L21/823437 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/66553 , H01L29/66583 , H01L29/66772 , H01L29/78648 , H03K19/0948
摘要： An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.

6. 发明授权

US07652330B1 Independently-double-gated combinational logic 有权
标题翻译：独立双门组合逻辑
公开(公告)号：US07652330B1
公开(公告)日：2010-01-26
申请号：US11306736
申请日：2006-01-09
申请人： Douglas R. Hackler, Sr. , Stephen A. Parke
发明人： Douglas R. Hackler, Sr. , Stephen A. Parke
IPC分类号： H01L27/01 , H01L27/12
CPC分类号： H01L21/2256 , H01L21/823437 , H01L21/84 , H01L27/088 , H01L27/092 , H01L27/1203 , H01L29/66553 , H01L29/66583 , H01L29/66772 , H01L29/7832 , H01L29/78648 , H03K19/0948
摘要： A family of logic circuits is constructed from double-gated four terminal transistors having independent gate control. First and second inputs to each logic element are independently coupled to the top and bottom gates of a transistor. The output voltage developed at either the source or drain represents an output logic state value according to the designed logic element. In a dynamic configuration the drain is precharged to an appropriate voltage. Complementary static CMOS configurations are also shown. Bottom Gates not driven by logic inputs or control signals may be biased to control the speed and power of the described logic circuits. Specific designs are given for AND, NAND, XOR, XNOR, OR and NOR combinational logic elements.
摘要翻译：逻辑电路系列由具有独立门控制的双门控四端子晶体管构成。每个逻辑元件的第一和第二输入独立地耦合到晶体管的顶部和底部栅极。在源极或漏极处产生的输出电压表示根据设计的逻辑元件的输出逻辑状态值。在动态配置中，漏极被预充电到适当的电压。还显示了互补静态CMOS配置。不由逻辑输入或控制信号驱动的底栅可能被偏置以控制所描述的逻辑电路的速度和功率。给出了AND，NAND，XOR，XNOR，OR和NOR组合逻辑元件的具体设计。

7. 发明授权

US07898009B2 Independently-double-gated transistor memory (IDGM) 有权
标题翻译：独立双门控晶体管存储器（IDGM）
公开(公告)号：US07898009B2
公开(公告)日：2011-03-01
申请号：US11678026
申请日：2007-02-22
申请人： Dale G. Wilson , Kelly James DeGregorio , Stephen A. Parke , Douglas R. Hackler, Sr.
发明人： Dale G. Wilson , Kelly James DeGregorio , Stephen A. Parke , Douglas R. Hackler, Sr.
IPC分类号： H01L29/80
CPC分类号： H01L27/1203 , G11C11/22 , G11C11/223 , H01L27/11585
摘要： Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
摘要翻译：存储单元由具有独立门控制的双门控四端子晶体管构成。 DRAM单元可以使用一个，两个或三个晶体管。单晶体管单元被构造为具有或不具有位存储电容器，并且描述NAND和NOR型非易失性NVRAM单元以及铁电FeRAM单元。对于所有电池，顶门提供常规接入，而独立的底栅提供控制以优化给定速度和功率参数的存储器保持以及适应对辐射的硬化。在没有电容器的单个晶体管电池中，使用底部栅极可以将密封包装到接近2 F2的密度。使用铁电材料作为栅极绝缘体产生单晶体管FeRAM单元，其克服了行业范围的写入干扰问题。存储单元与SOI逻辑电路兼容，用作SOC应用中的嵌入式RAM。

8. 发明授权

US07015547B2 Multi-configurable independently multi-gated MOSFET 有权
标题翻译：多配置独立多门控MOSFET
公开(公告)号：US07015547B2
公开(公告)日：2006-03-21
申请号：US10613169
申请日：2003-07-03
申请人： Douglas R. Hackler, Sr. , Stephen A. Parke
发明人： Douglas R. Hackler, Sr. , Stephen A. Parke
IPC分类号： H01L27/01 , H01L27/12
CPC分类号： H01L29/7832 , H01L21/2256 , H01L21/823437 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/66553 , H01L29/66583 , H01L29/66772 , H01L29/78648 , H01L2924/0002 , H03K19/0948 , H01L2924/00
摘要： A double-gated transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain and further resist compression of the channel by the source and drain.
摘要翻译：双门控晶体管架构提供用于独立门控制的四终端器件，浮体器件和动态阈值器件。通道可以具有U形横截面积以增加通道长度和门控制。第一和第二绝缘间隔物设置在顶部栅极的相对侧上，使得第一间隔物位于源极和顶部栅极之间，而第二间隔物位于漏极和顶部栅极之间。源极和漏极包括靠近间隔物延伸并连接到沟道的延伸部分。间隔物屏蔽通道与源极和漏极的场效应，并进一步抵抗通过源极和漏极压缩沟道。

9. 发明申请

US20080203443A1 Independently-Double-Gated Transistor Memory (IDGM) 有权
标题翻译：独立双门限晶体管内存（IDGM）
公开(公告)号：US20080203443A1
公开(公告)日：2008-08-28
申请号：US11678026
申请日：2007-02-22
申请人： Dale G. Wilson , Kelly J. DeGregorio , Stephen A. Parke , Douglas R. Hackler
发明人： Dale G. Wilson , Kelly J. DeGregorio , Stephen A. Parke , Douglas R. Hackler
IPC分类号： H01L27/108
CPC分类号： H01L27/1203 , G11C11/22 , G11C11/223 , H01L27/11585
摘要： Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
摘要翻译：存储单元由具有独立门控制的双门控四端子晶体管构成。 DRAM单元可以使用一个，两个或三个晶体管。单晶体管单元被构造为具有或不具有位存储电容器，并且描述NAND和NOR型非易失性NVRAM单元以及铁电FeRAM单元。对于所有电池，顶门提供常规接入，而独立的底栅提供控制以优化给定速度和功率参数的存储器保持以及适应对辐射的硬化。在没有电容器的单个晶体管电池中，使用底部栅极可使封装密度接近2F 2。使用铁电材料作为栅极绝缘体产生单晶体管FeRAM单元，其克服了行业范围的写入干扰问题。存储单元与SOI逻辑电路兼容，用作SOC应用中的嵌入式RAM。

10. 发明授权

US06580137B2 Damascene double gated transistors and related manufacturing methods 失效
公开(公告)号：US06580137B2
公开(公告)日：2003-06-17
申请号：US09942533
申请日：2001-08-29
申请人： Stephen A. Parke
发明人： Stephen A. Parke
IPC分类号： H01L21336
CPC分类号： H01L29/7802 , H01L21/28194 , H01L21/84 , H01L27/1203 , H01L29/1087 , H01L29/41766 , H01L29/4908 , H01L29/517 , H01L29/66477 , H01L29/66484 , H01L29/66537 , H01L29/66553 , H01L29/66621 , H01L29/66742 , H01L29/66772 , H01L29/7832 , H01L29/7841 , H01L29/78612 , H01L29/78618 , H01L29/78645 , H01L29/78648
摘要： This invention provides the structure and fabrication process of a completely planar, Damascene double gated transistor. The structure has a novel self-aligned, hyper-abrupt retrograde body and a zero-parasitic, endwall gate-body connection. The structure provides for increased density and enables ultra low power to be utilized. The methods also provide for simultaneously making both four-terminal and dynamic threshold MOSFET devices.

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