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1. 发明授权

US07898009B2 Independently-double-gated transistor memory (IDGM) 有权
标题翻译：独立双门控晶体管存储器（IDGM）
公开(公告)号：US07898009B2
公开(公告)日：2011-03-01
申请号：US11678026
申请日：2007-02-22
申请人： Dale G. Wilson , Kelly James DeGregorio , Stephen A. Parke , Douglas R. Hackler, Sr.
发明人： Dale G. Wilson , Kelly James DeGregorio , Stephen A. Parke , Douglas R. Hackler, Sr.
IPC分类号： H01L29/80
CPC分类号： H01L27/1203 , G11C11/22 , G11C11/223 , H01L27/11585
摘要： Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
摘要翻译：存储单元由具有独立门控制的双门控四端子晶体管构成。 DRAM单元可以使用一个，两个或三个晶体管。单晶体管单元被构造为具有或不具有位存储电容器，并且描述NAND和NOR型非易失性NVRAM单元以及铁电FeRAM单元。对于所有电池，顶门提供常规接入，而独立的底栅提供控制以优化给定速度和功率参数的存储器保持以及适应对辐射的硬化。在没有电容器的单个晶体管电池中，使用底部栅极可以将密封包装到接近2 F2的密度。使用铁电材料作为栅极绝缘体产生单晶体管FeRAM单元，其克服了行业范围的写入干扰问题。存储单元与SOI逻辑电路兼容，用作SOC应用中的嵌入式RAM。

2. 发明授权

US08148759B2 Single transistor memory with immunity to write disturb 有权
标题翻译：单晶体管存储器具有写入干扰的抗扰度
公开(公告)号：US08148759B2
公开(公告)日：2012-04-03
申请号：US13036735
申请日：2011-02-28
申请人： Dale G. Wilson , Douglas R. Hackler, Sr.
发明人： Dale G. Wilson , Douglas R. Hackler, Sr.
IPC分类号： H01L29/80
CPC分类号： H01L27/1203 , G11C11/22 , G11C11/223 , H01L27/11585
摘要： Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells using one transistor to implement a Ferroelectric FeRAM are described. Top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
摘要翻译：存储单元由具有独立门控制的双门控四端子晶体管构成。描述了使用一个晶体管来实现铁电FeRAM的DRAM单元。顶门提供常规访问，而独立的底栅提供控制以优化给定速度和功率参数的存储器保持以及适应对辐射的硬化。在没有电容器的单个晶体管电池中，使用底部栅极可以将密封包装到接近2 F2的密度。使用铁电材料作为栅极绝缘体产生单晶体管FeRAM单元，其克服了行业范围的写入干扰问题。存储单元与SOI逻辑电路兼容，用作SOC应用中的嵌入式RAM。

3. 发明申请

US20110147806A1 Double-Gated Transistor Memory 有权
标题翻译：双门极晶体管内存
公开(公告)号：US20110147806A1
公开(公告)日：2011-06-23
申请号：US13036807
申请日：2011-02-28
申请人： Dale G. Wilson , Douglas R. Hackler, SR.
发明人： Dale G. Wilson , Douglas R. Hackler, SR.
IPC分类号： H01L29/788 , H01L27/115
CPC分类号： H01L27/1203 , G11C11/22 , G11C11/223 , H01L27/11585
摘要： Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
摘要翻译：存储单元由具有独立门控制的双门控四端子晶体管构成。 DRAM单元可以使用一个，两个或三个晶体管。单晶体管单元被构造为具有或不具有位存储电容器，并且描述NAND和NOR型非易失性NVRAM单元以及铁电FeRAM单元。对于所有电池，顶门提供常规接入，而独立的底栅提供控制以优化给定速度和功率参数的存储器保持以及适应对辐射的硬化。在没有电容器的单个晶体管电池中，使用底部栅极可以将密封包装到接近2 F2的密度。存储单元与SOI逻辑电路兼容，用作SOC应用中的嵌入式RAM。

4. 发明申请

US20140264938A1 Flexible Interconnect 审中-公开
标题翻译：灵活互连
公开(公告)号：US20140264938A1
公开(公告)日：2014-09-18
申请号：US14213417
申请日：2014-03-14
申请人： Douglas R. Hackler, SR. , Dale G. Wilson
发明人： Douglas R. Hackler, SR. , Dale G. Wilson
IPC分类号： H01L23/48
CPC分类号： H01L24/50 , H01L24/86 , H01L2924/01322 , H01L2924/07802 , H01L2924/00
摘要： The described Flexible Interconnect is useful for making electrical or other contact between various combinations of semiconductor die, printed circuit boards and other components. A thin flexible material, such as a polymer, supports printed lines that connect pads which may contain vias. The flexible interconnect can be attached using conductive and non-conductive epoxies to the components that are to be interconnected. Each interconnect can be individually insulated from adjacent interconnects, so that it can be deformed and flexed without making contact with another. The described interconnects can span long distances and conform to underlying topography. Metal interconnects may be used to conduct heat or to form heat sinks. Similarly, flexible interconnects may be formed from material that is an electrical insulator but thermally conductive in order to transport heat away from the attached circuitry. Optical conductors may be supported for use as flexible photonic waveguides.
摘要翻译：所描述的柔性互连可用于在半导体管芯，印刷电路板和其他部件的各种组合之间进行电气或其他接触。诸如聚合物的薄柔性材料支持连接可能包含通孔的焊盘的印刷线。柔性互连可以使用导电和非导电环氧树脂附着到待互连的部件上。每个互连可以与相邻的互连单独绝缘，使得其可以变形和弯曲而不与另一个相接触。所描述的互连可以跨越长距离并且符合底层的地形。金属互连可用于传导热量或形成散热片。类似地，柔性互连可以由作为电绝缘体的材料形成，但是导热以便将热量从附接的电路传送出去。光导体可以被支持用作柔性光子波导。

5. 发明申请

US20140224882A1 Flexible Smart Card Transponder 审中-公开
标题翻译：灵活智能卡转发器
公开(公告)号：US20140224882A1
公开(公告)日：2014-08-14
申请号：US14181539
申请日：2014-02-14
申请人： Douglas R. Hackler, SR. , Dale G. Wilson
发明人： Douglas R. Hackler, SR. , Dale G. Wilson
IPC分类号： G06K19/077
CPC分类号： G06K19/0779 , G06K19/025
摘要： This smart card transponder is made extremely flexible by being ultrathin. Its thickness of only 0.25 mm is achieved by using all ultrathin flexible substrates. A Semiconductor-on-Polymer (SOP) process creates flexible integrated circuit (IC) components which are applied to a flexible antenna substrate. With suitable selection of materials, no additional substrates are required. The antenna substrate may be a thin PVC or even paper. The antenna is printed directly onto the substrate using conductive ink. Passive components such as resistors, capacitors, inductors and delay lines are also formed from conductive ink as appropriate to the circuit being implemented. Interconnections between components are created in a similar process. The ultrathin SOP ICs require no bonding wires since their contact pads are readily accessible for attachment to the interconnects through conductive epoxy. Extreme flexibility of all componentry enhances reliability while enabling inclusion of larger, more complex ICs.
摘要翻译：该智能卡转发器通过超薄使其非常灵活。其厚度仅为0.25毫米，通过使用所有超薄柔性基板实现。聚合物半导体（SOP）工艺创建应用于柔性天线基板的灵活的集成电路（IC）组件。通过合适的材料选择，不需要额外的基材。天线基板可以是薄PVC或甚至纸。使用导电油墨将天线直接印刷到基板上。诸如电阻器，电容器，电感器和延迟线的被动元件也由导电墨水形成，适用于所实施的电路。组件之间的互连以类似的过程创建。超薄SOP IC不需要接合线，因为它们的接触垫易于通过导电环氧树脂连接到互连件上。所有组件的极大的灵活性增强了可靠性，同时能够包含更大，更复杂的IC。

6. 发明授权

US08089108B2 Double-gated transistor memory 有权
标题翻译：双门控晶体管存储器
公开(公告)号：US08089108B2
公开(公告)日：2012-01-03
申请号：US13036807
申请日：2011-02-28
申请人： Dale G. Wilson , Douglas R. Hackler, Sr.
发明人： Dale G. Wilson , Douglas R. Hackler, Sr.
IPC分类号： H01L29/80
CPC分类号： H01L27/1203 , G11C11/22 , G11C11/223 , H01L27/11585
摘要： Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
摘要翻译：存储单元由具有独立门控制的双门控四端子晶体管构成。 DRAM单元可以使用一个，两个或三个晶体管。单晶体管单元被构造为具有或不具有位存储电容器，并且描述NAND和NOR型非易失性NVRAM单元以及铁电FeRAM单元。对于所有电池，顶门提供常规接入，而独立的底栅提供控制以优化给定速度和功率参数的存储器保持以及适应对辐射的硬化。在没有电容器的单个晶体管电池中，使用底部栅极可以将密封包装到接近2 F2的密度。存储单元与SOI逻辑电路兼容，用作SOC应用中的嵌入式RAM。

7. 发明授权

US09733428B2 Flexible 3-D photonic device 有权
公开(公告)号：US09733428B2
公开(公告)日：2017-08-15
申请号：US14172724
申请日：2014-02-04
申请人： Douglas R. Hackler, Sr. , Dale G. Wilson
发明人： Douglas R. Hackler, Sr. , Dale G. Wilson
IPC分类号： G02B6/122 , G02B6/13 , G02B6/12
CPC分类号： G02B6/122 , G02B6/1221 , G02B6/13 , G02B2006/12061
摘要： Three-dimensional flexible photonic integrated circuits on silicon are fabricated in semiconductor wafer form and then transferred to Silicon-on-Polymer (SOP) substrates. SOP provides flexibility for conformal mounting with devices capable of maintaining performance when dynamically deformed to allow routing of light in x, y and z directions. Bonding a wafer or individual die of III-V semiconductor, such as Gallium Arsenide or similar photonic material, to the flexible silicon creates an active region for lasers, amplifiers, modulators, and other photonic devices using standard processing. Mounting additional photonic devices to the opposite side of a flexible photonic waveguide produces a stack for three-dimensional devices. Multiple flexible photonic waveguides may be stacked to increase functionality by transferring light between stacked waveguides. The flexible photonic circuit allows for integration of photonic devices such as low threshold lasers, tunable lasers, and other photonic integrated circuits with flexible Complementary Metal Oxide Semiconductor (CMOS) integrated circuits.

8. 发明授权

US09209047B1 Method of producing encapsulated IC devices on a wafer 有权
标题翻译：在晶片上制造封装的IC器件的方法
公开(公告)号：US09209047B1
公开(公告)日：2015-12-08
申请号：US14223895
申请日：2014-03-24
申请人： Douglas R. Hackler, Sr. , Dale G. Wilson
发明人： Douglas R. Hackler, Sr. , Dale G. Wilson
IPC分类号： H01L21/56 , H01L23/31
CPC分类号： H01L21/561 , H01L21/568 , H01L21/6835 , H01L21/6836 , H01L21/78 , H01L21/784 , H01L23/3135 , H01L24/25 , H01L24/82 , H01L24/96 , H01L24/97 , H01L2221/68327 , H01L2221/6834 , H01L2224/04105 , H01L2224/2518 , H01L2224/82005 , H01L2224/8203 , H01L2224/94 , H01L2224/03
摘要： This method of waferscale packaging produces finished integrated circuits (ICs) individually completely encapsulated with environmentally protective packaging material while still in the wafer format. Following conventional semiconductor fabrication of chips at the wafer level and prior to their separation, a first polymer is applied to the front surface of the wafer with allowance for contact holes. A carrier wafer is attached to the exposed polymer. The original substrate is removed and the devices are separated by cutting through the semiconductor layer and the first polymer. A second polymer is applied to cover the exposed backside of the devices and to fill the cut spaces between them, thereby sealing the remaining five surfaces of the chips. The second polymer layer may also include contact holes for access to the back side of the device chips. A second singulation cutting leaves the chips on the wafer prepared for a pick-and-place operation.
摘要翻译：这种晶片封装的方法产生完全用环保包装材料完全封装的成品集成电路（IC），同时仍然是晶片格式。按照常规半导体制造芯片在晶片级别并在分离之前，第一聚合物被施加到晶片的正面以允许接触孔。载体晶片附着在暴露的聚合物上。去除原始衬底，并且通过切割半导体层和第一聚合物来分离器件。施加第二聚合物以覆盖设备的暴露的背面并填充它们之间的切割空间，从而密封芯片的剩余的五个表面。第二聚合物层还可以包括用于接近器件芯片背面的接触孔。第二次切割将晶片上的芯片留在准备进行拾取和放置操作的晶片上。

9. 发明申请

US20140219604A1 Flexible 3-D Photonic Device 审中-公开
标题翻译：灵活的3-D光子器件
公开(公告)号：US20140219604A1
公开(公告)日：2014-08-07
申请号：US14172724
申请日：2014-02-04
申请人： Douglas R. Hackler, Sr. , Dale G. Wilson
发明人： Douglas R. Hackler, Sr. , Dale G. Wilson
IPC分类号： G02B6/12
CPC分类号： G02B6/122 , G02B6/1221 , G02B6/13 , G02B2006/12061
摘要： Three-dimensional flexible photonic integrated circuits on silicon are fabricated in semiconductor wafer form and then transferred to Silicon-on-Polymer (SOP) substrates. SOP provides flexibility for conformal mounting with devices capable of maintaining performance when dynamically deformed to allow routing of light in x, y and z directions. Bonding a wafer or individual die of III-V semiconductor, such as Gallium Arsenide or similar photonic material, to the flexible silicon creates an active region for lasers, amplifiers, modulators, and other photonic devices using standard processing. Mounting additional photonic devices to the opposite side of a flexible photonic waveguide produces a stack for three-dimensional devices. Multiple flexible photonic waveguides may be stacked to increase functionality by transferring light between stacked waveguides. The flexible photonic circuit allows for integration of photonic devices such as low threshold lasers, tunable lasers, and other photonic integrated circuits with flexible Complementary Metal Oxide Semiconductor (CMOS) integrated circuits.
摘要翻译：硅上的三维柔性光子集成电路以半导体晶片形式制造，然后转移到硅聚合物（SOP）基板上。 SOP提供了灵活性，以便在动态变形时能够保持性能的设备进行共形安装，以允许在x，y和z方向上布置光。将诸如砷化镓或类似光子材料的III-V半导体的晶片或单个晶片结合到柔性硅，使用标准处理为激光器，放大器，调制器和其他光子器件创建有源区域。将另外的光子器件安装到柔性光子波导的相对侧产生用于三维器件的堆叠。可以堆叠多个柔性光子波导以通过在堆叠的波导之间传送光来增加功能。柔性光子电路允许诸如低阈值激光器，可调谐激光器和具有柔性互补金属氧化物半导体（CMOS）集成电路的其它光子集成电路的光子器件的集成。

10. 发明申请

US20110147807A1 Single Transistor Memory with Immunity to Write Disturb 有权
标题翻译：具有抗干扰写入干扰的单晶体管存储器
公开(公告)号：US20110147807A1
公开(公告)日：2011-06-23
申请号：US13036735
申请日：2011-02-28
申请人： Dale G. Wilson , Douglas R. Hackler, SR.
发明人： Dale G. Wilson , Douglas R. Hackler, SR.
IPC分类号： H01L29/808
CPC分类号： H01L27/1203 , G11C11/22 , G11C11/223 , H01L27/11585
摘要： Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells using one transistor to implement a Ferroelectric FeRAM are described. Top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. Using a ferroelectric material as the gate insulator produces a single-transistor FeRAM cell that overcomes the industry-wide Write Disturb problem. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
摘要翻译：存储单元由具有独立门控制的双门控四端子晶体管构成。描述了使用一个晶体管来实现铁电FeRAM的DRAM单元。顶门提供常规访问，而独立的底栅提供控制以优化给定速度和功率参数的存储器保持以及适应对辐射的硬化。在没有电容器的单个晶体管电池中，使用底部栅极可以将密封包装到接近2 F2的密度。使用铁电材料作为栅极绝缘体产生单晶体管FeRAM单元，其克服了行业范围的写入干扰问题。存储单元与SOI逻辑电路兼容，用作SOC应用中的嵌入式RAM。

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