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1. 发明授权

US11735464B1 Method of demounting thin semiconductor devices 有权
公开(公告)号：US11735464B1
公开(公告)日：2023-08-22
申请号：US17407760
申请日：2021-08-20
申请人： Douglas R. Hackler, Sr. , Randall S. Parker
发明人： Douglas R. Hackler, Sr. , Randall S. Parker
IPC分类号： H01L21/683
CPC分类号： H01L21/6836 , H01L2221/68336 , H01L2221/68354 , H01L2221/68386
摘要： The described method enables removal of any flexible material from a temporary carrier for transfer to another surface. In particular, a semiconductor wafer is commonly held by a temporary adhesive to a carrier substrate for support during a variety of processing steps, including thinning of the semiconductor device layer. Subsequent to processing, the described method attaches the ultra-thin device layer to a roll of tape for removal from the temporary adhesive, followed by transfer to a demount roller, which then releases it onto a desired permanent surface. Utilizing the flexible nature of the ultra-thin device layer, the sequence of rollers is able to peel it from the temporary adhesive without any need for laser release processing or chemical adhesive removal while maintaining the thinned wafer in a planar form during processing. This transfer supports operations that include a change of orientation, such as from face up to face down.

2. 发明授权

US09082881B1 Semiconductor on polymer substrate 有权
标题翻译：聚合物基板上的半导体
公开(公告)号：US09082881B1
公开(公告)日：2015-07-14
申请号：US13936937
申请日：2013-07-08
申请人： Douglas R. Hackler, Sr. , Richard L. Chaney
发明人： Douglas R. Hackler, Sr. , Richard L. Chaney
IPC分类号： H01L23/48 , H01L21/84 , H01L29/02
CPC分类号： H01L21/84 , H01L21/6835 , H01L21/7806 , H01L29/02 , H01L2221/68327 , H01L2221/68368
摘要： Semiconductor On Polymer (SOP) is a flexible ultra-thin substrate that can be used as the starting material for CMOS, MEMS or Complex Interconnects such as an interposer. The described process results in a flexible SOP device with open bond pads. After deposition of a liquid polymer onto a semiconductor substrate, the polymer is converted to a solid, creating a new substrate that is temporarily bonded to a carrier wafer. The semiconductor layer is then etched to be ultra-thin and highly uniform, specifically, a single crystalline silicon layer. Following fabrication of devices and interconnects on the polymer substrate, the ultra thin wafer is released from the carrier wafer in substrate form to be used whole or tiled for subsequent assembly. Among other advantages, the flexible format of the SOP substrate enables low resistance 3-D interconnects, and provides for a significant increase in performance due to a reduction in parasitic capacitance.
摘要翻译：半导体聚合物（SOP）是一种灵活的超薄基板，可用作CMOS，MEMS或复杂互连（如内插器）的起始材料。所描述的过程产生具有开放接合焊盘的柔性SOP器件。在液体聚合物沉积到半导体衬底上之后，聚合物被转化为固体，产生临时结合到载体晶片的新衬底。然后将半导体层蚀刻成超薄且高度均匀，特别是单晶硅层。在聚合物基板上制造器件和互连之后，超薄晶片以基板形式从载体晶片释放出来，以便整体使用或平铺以用于随后的组装。除了其他优点之外，SOP衬底的灵活形式能够实现低电阻3-D互连，并且由于寄生电容的减小而提供了性能的显着增加。

3. 发明授权

US07518189B1 Independently-double-gated field effect transistor 有权
标题翻译：独立双门控场效应晶体管
公开(公告)号：US07518189B1
公开(公告)日：2009-04-14
申请号：US11307863
申请日：2006-02-25
申请人： Douglas R. Hackler, Sr. , Stephen A. Parke
发明人： Douglas R. Hackler, Sr. , Stephen A. Parke
IPC分类号： H01L29/94
CPC分类号： H01L21/2256 , H01L21/823437 , H01L21/84 , H01L27/088 , H01L27/098 , H01L27/1203 , H01L29/4908 , H01L29/66484 , H01L29/66553 , H01L29/66583 , H01L29/66772 , H01L29/7832 , H01L29/78621 , H01L29/78648 , H01L29/8086 , H01L29/8124 , H03K19/0948
摘要： This independent double-gated transistor architecture creates a MOSFET, JFET or MESFET in parallel with a JFET. Its two gates may be configured to provide a four-terminal device for independent gate control, a floating gate device, and a double-gate device. First and second insulating spacers are disposed on opposing sides of the top gate with the first spacer between the source and the top gate and the second spacer between the drain and the top gate. Source and drain extensions extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain and further resist compression of the channel by the source and drain. Truly independent control of the two gates makes possible many 2-, 3- and 4-terminal device configurations that may be dynamically reconfigured to trade off speed against power. The resulting transistors exhibit inherent radiation tolerance.
摘要翻译：这种独立的双门控晶体管架构与JFET并联产生MOSFET，JFET或MESFET。其两个门可以被配置为提供用于独立门控制的四端子器件，浮动栅极器件和双栅极器件。第一和第二绝缘间隔物设置在顶部栅极的相对侧上，第一间隔物在源极和顶部栅极之间，第二间隔物位于漏极和顶部栅极之间。源极和漏极延伸部分靠近间隔件延伸并耦合到通道。间隔物屏蔽通道与源极和漏极的场效应，并进一步抵抗通过源极和漏极压缩沟道。对两个门的真正的独立控制使得许多可以被动态重新配置的两个，三个和四个终端设备配置成为能够抵消电力的速度。所得的晶体管表现出固有的辐射耐受性。

4. 发明授权

US07019342B2 Double-gated transistor circuit 有权
标题翻译：双门控晶体管电路
公开(公告)号：US07019342B2
公开(公告)日：2006-03-28
申请号：US10719119
申请日：2003-11-21
申请人： Douglas R. Hackler, Sr. , Stephen A. Parke
发明人： Douglas R. Hackler, Sr. , Stephen A. Parke
IPC分类号： H01L27/148 , H01L29/768
CPC分类号： H01L29/7832 , H01L21/2256 , H01L21/823437 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/66553 , H01L29/66583 , H01L29/66772 , H01L29/78648 , H03K19/0948
摘要： An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.
摘要翻译： OR门电路包括具有独立门控制的双门控四端子晶体管。第一和第二输入独立地耦合到晶体管的顶部和底部栅极。漏极耦合到输出并预充电到低电压。输入到顶部或底部栅极导致漏极的高电压，输出值为1。

5. 发明授权

US06919647B2 SRAM cell 有权
标题翻译： SRAM单元
公开(公告)号：US06919647B2
公开(公告)日：2005-07-19
申请号：US10733612
申请日：2003-12-11
申请人： Douglas R. Hackler, Sr. , Stephen A. Parke , Kelly James Degregorio
发明人： Douglas R. Hackler, Sr. , Stephen A. Parke , Kelly James Degregorio
IPC分类号： H01L21/225 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/088 , H01L27/12 , H01L29/786 , H03K19/0948 , H01L27/11
CPC分类号： H01L21/2256 , H01L21/823437 , H01L21/84 , H01L27/088 , H01L27/1203 , H01L29/66553 , H01L29/66583 , H01L29/66772 , H01L29/7832 , H01L29/78648 , H03K19/0948 , Y10S257/903
摘要： A SRAM cell includes double-gated PMOS and NMOS transistors to form a latch and retain a value. The unique MOSFET transistor architecture provides a four terminal device for independent gate control, a floating body device, and a dynamic threshold device. The channel may have a U-shaped cross-sectional area to increase the channel length and gate control. First and second insulating spacers are disposed on opposing sides of the top gate such that the first spacer is between the source and the top gate, and the second spacer is between the drain and the top gate. The source and drain include extensions that extend proximate to the spacers and couple to the channel. The spacers shield the channel from the field effect of the source and drain, and further resist compression of the channel by the source and drain.
摘要翻译： SRAM单元包括双门控PMOS和NMOS晶体管，以形成锁存器并保持一个值。独特的MOSFET晶体管架构提供了一个用于独立门控制的四端子器件，一个浮体器件和一个动态阈值器件。通道可以具有U形横截面积以增加通道长度和门控制。第一和第二绝缘间隔物设置在顶部栅极的相对侧上，使得第一间隔物在源极和顶部栅极之间，并且第二间隔物位于漏极和顶部栅极之间。源极和漏极包括靠近间隔物延伸并连接到沟道的延伸部分。间隔件将通道与源极和漏极的场效应隔离，并进一步抵抗通过源极和漏极的通道的压缩。

6. 发明授权

US08913402B1 Triple-damascene interposer 有权
标题翻译：三重镶嵌插件
公开(公告)号：US08913402B1
公开(公告)日：2014-12-16
申请号：US13112450
申请日：2011-05-20
申请人： John E. Berg , Douglas R. Hackler, Sr.
发明人： John E. Berg , Douglas R. Hackler, Sr.
IPC分类号： H05K1/11 , H05K7/00 , H05K1/18 , H05K1/00
CPC分类号： H05K7/1061 , B81C1/00238 , B81C2203/0792 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L23/5223 , H01L23/5227 , H01L23/5228 , H01L24/06 , H01L24/16 , H01L24/17 , H01L25/0657 , H01L2221/68327 , H01L2224/03002 , H01L2224/0401 , H01L2224/05567 , H01L2224/0557 , H01L2224/06181 , H01L2224/16147 , H01L2224/17181 , H01L2225/06513 , H01L2225/06517 , H01L2225/06541 , H01L2225/06572 , H01L2924/14 , H01L2924/1434 , H01L2924/1461 , H01L2924/157 , H01L2924/15787
摘要： This interposer provides interconnections between stacked layers of circuits, which may include integrated circuits, PC boards, and hybrid substrates. Fabricated as an integrated circuit itself using readily available process steps, this interposer uses single and dual-damascene layers to increase the density of usable interconnections on both its top and bottom surfaces. Access from a top surface to a bottom surface is provided by conductive through-vias that may be placed at a high density. For even greater density, interconnections may be routed within silicon trenches, while damascene processing reduces the total number of steps required for fabrication. The described techniques may be used to create double-sided integrated circuits.
摘要翻译：该插入器提供堆叠的电路层之间的互连，其可以包括集成电路，PC板和混合基板。该插入器使用易于获得的工艺步骤作为集成电路本身，使用单镶嵌层和双镶嵌层来增加其顶表面和底表面上的可用互连的密度。从顶表面到底表面的访问由可以高密度放置的导电通孔提供。对于更大的密度，互连可以在硅沟槽内布线，而镶嵌处理减少了制造所需的步骤总数。所描述的技术可以用于创建双面集成电路。

7. 发明申请

US20140264938A1 Flexible Interconnect 审中-公开
标题翻译：灵活互连
公开(公告)号：US20140264938A1
公开(公告)日：2014-09-18
申请号：US14213417
申请日：2014-03-14
申请人： Douglas R. Hackler, SR. , Dale G. Wilson
发明人： Douglas R. Hackler, SR. , Dale G. Wilson
IPC分类号： H01L23/48
CPC分类号： H01L24/50 , H01L24/86 , H01L2924/01322 , H01L2924/07802 , H01L2924/00
摘要： The described Flexible Interconnect is useful for making electrical or other contact between various combinations of semiconductor die, printed circuit boards and other components. A thin flexible material, such as a polymer, supports printed lines that connect pads which may contain vias. The flexible interconnect can be attached using conductive and non-conductive epoxies to the components that are to be interconnected. Each interconnect can be individually insulated from adjacent interconnects, so that it can be deformed and flexed without making contact with another. The described interconnects can span long distances and conform to underlying topography. Metal interconnects may be used to conduct heat or to form heat sinks. Similarly, flexible interconnects may be formed from material that is an electrical insulator but thermally conductive in order to transport heat away from the attached circuitry. Optical conductors may be supported for use as flexible photonic waveguides.
摘要翻译：所描述的柔性互连可用于在半导体管芯，印刷电路板和其他部件的各种组合之间进行电气或其他接触。诸如聚合物的薄柔性材料支持连接可能包含通孔的焊盘的印刷线。柔性互连可以使用导电和非导电环氧树脂附着到待互连的部件上。每个互连可以与相邻的互连单独绝缘，使得其可以变形和弯曲而不与另一个相接触。所描述的互连可以跨越长距离并且符合底层的地形。金属互连可用于传导热量或形成散热片。类似地，柔性互连可以由作为电绝缘体的材料形成，但是导热以便将热量从附接的电路传送出去。光导体可以被支持用作柔性光子波导。

8. 发明申请

US20140224882A1 Flexible Smart Card Transponder 审中-公开
标题翻译：灵活智能卡转发器
公开(公告)号：US20140224882A1
公开(公告)日：2014-08-14
申请号：US14181539
申请日：2014-02-14
申请人： Douglas R. Hackler, SR. , Dale G. Wilson
发明人： Douglas R. Hackler, SR. , Dale G. Wilson
IPC分类号： G06K19/077
CPC分类号： G06K19/0779 , G06K19/025
摘要： This smart card transponder is made extremely flexible by being ultrathin. Its thickness of only 0.25 mm is achieved by using all ultrathin flexible substrates. A Semiconductor-on-Polymer (SOP) process creates flexible integrated circuit (IC) components which are applied to a flexible antenna substrate. With suitable selection of materials, no additional substrates are required. The antenna substrate may be a thin PVC or even paper. The antenna is printed directly onto the substrate using conductive ink. Passive components such as resistors, capacitors, inductors and delay lines are also formed from conductive ink as appropriate to the circuit being implemented. Interconnections between components are created in a similar process. The ultrathin SOP ICs require no bonding wires since their contact pads are readily accessible for attachment to the interconnects through conductive epoxy. Extreme flexibility of all componentry enhances reliability while enabling inclusion of larger, more complex ICs.
摘要翻译：该智能卡转发器通过超薄使其非常灵活。其厚度仅为0.25毫米，通过使用所有超薄柔性基板实现。聚合物半导体（SOP）工艺创建应用于柔性天线基板的灵活的集成电路（IC）组件。通过合适的材料选择，不需要额外的基材。天线基板可以是薄PVC或甚至纸。使用导电油墨将天线直接印刷到基板上。诸如电阻器，电容器，电感器和延迟线的被动元件也由导电墨水形成，适用于所实施的电路。组件之间的互连以类似的过程创建。超薄SOP IC不需要接合线，因为它们的接触垫易于通过导电环氧树脂连接到互连件上。所有组件的极大的灵活性增强了可靠性，同时能够包含更大，更复杂的IC。

9. 发明授权

US08089108B2 Double-gated transistor memory 有权
标题翻译：双门控晶体管存储器
公开(公告)号：US08089108B2
公开(公告)日：2012-01-03
申请号：US13036807
申请日：2011-02-28
申请人： Dale G. Wilson , Douglas R. Hackler, Sr.
发明人： Dale G. Wilson , Douglas R. Hackler, Sr.
IPC分类号： H01L29/80
CPC分类号： H01L27/1203 , G11C11/22 , G11C11/223 , H01L27/11585
摘要： Memory cells are constructed from double-gated four terminal transistors having independent gate control. DRAM cells may use one, two or three transistors. Single transistor cells are constructed either with or without a bit storage capacitor, and both NAND- and NOR-type Non-Volatile NVRAM cells, as well as Ferroelectric FeRAM cells, are described. For all cells, top gates provide conventional access while independent bottom gates provide control to optimize memory retention for given speed and power parameters as well as to accommodate hardening against radiation. In a single transistor cell without a capacitor, use of the bottom gate allows packing to a density approaching 2 F2. The memory cells are compatible with SOI logic circuitry for use as embedded RAM in SOC applications.
摘要翻译：存储单元由具有独立门控制的双门控四端子晶体管构成。 DRAM单元可以使用一个，两个或三个晶体管。单晶体管单元被构造为具有或不具有位存储电容器，并且描述NAND和NOR型非易失性NVRAM单元以及铁电FeRAM单元。对于所有电池，顶门提供常规接入，而独立的底栅提供控制以优化给定速度和功率参数的存储器保持以及适应对辐射的硬化。在没有电容器的单个晶体管电池中，使用底部栅极可以将密封包装到接近2 F2的密度。存储单元与SOI逻辑电路兼容，用作SOC应用中的嵌入式RAM。

10. 发明授权

US08072006B1 Double-gated sensor cell 有权
标题翻译：双门传感器单元
公开(公告)号：US08072006B1
公开(公告)日：2011-12-06
申请号：US11306292
申请日：2005-12-21
申请人： Douglas R. Hackler, Sr. , Richard A. Hayhurst , Stephen A. Parke
发明人： Douglas R. Hackler, Sr. , Richard A. Hayhurst , Stephen A. Parke
IPC分类号： H01L29/76
CPC分类号： H01L27/14689
摘要： A high quality imager is constructed using a silicon-on-insulator (SOI) process with sensors fabricated in the SOI substrate and isolated by the buried oxide (BOX) from associated readout circuitry in the SOI layer. Handle windows are opened in the SOI device layer for fabrication of the sensors in the handle layer substrate and then closed prior to processing in the device layer. By keeping the buried oxide layer intact, the described technique allows for independent processing of sensors and readout circuitry so that each is optimized with regard to thermal and dopant properties without concern for degradation of the other. The process is compatible with the fabrication of readout circuitry using transistors having independent double-gates, which offer simultaneous advantages in scalability, low power and low noise. Photodiode sensors are shown with allowance for many other types of sensors. The process easily accommodates hardening against radiation.
摘要翻译：使用在SOI衬底中制造的传感器并通过SOI层中的相关读出电路的掩埋氧化物（BOX）隔离的传感器来构建使用绝缘体上硅（SOI）工艺的高质量成像器。处理窗在SOI器件层中打开，用于制造处理层衬底中的传感器，然后在器件层中处理之前封闭。通过保持掩埋氧化物层的完整性，所描述的技术允许传感器和读出电路的独立处理，使得每个都相对于热和掺杂剂性质而优化，而不考虑另一个的劣化。该过程与使用具有独立双栅极的晶体管的读出电路的制造兼容，其提供可扩展性，低功率和低噪声的同时优势。显示光电二极管传感器，允许许多其他类型的传感器。该过程容易适应辐射硬化。

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