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1. 发明授权

US06351797B1 Translation look-aside buffer for storing region configuration bits and method of operation 有权
标题翻译：用于存储区域配置位的翻译后备缓冲区和操作方法
公开(公告)号：US06351797B1
公开(公告)日：2002-02-26
申请号：US09192122
申请日：1998-11-13
申请人： Douglas R. Beard, Sr. , Darren Bensley , Daniel W. Green
发明人： Douglas R. Beard, Sr. , Darren Bensley , Daniel W. Green
IPC分类号： G06F1210
CPC分类号： G06F12/1027
摘要： There is disclosed, for use in an x86-compatible processor, a translation look-aside buffer (TLB) that stores region configuration bits (or attribute bits) associated with each physical address stored in the TLB and that makes the region configuration bits available at the same time that the physical address is generated/translated by the TLB. The TLB comprises: 1) a tag array capable of storing an untranslated address in one of N tag entries in the tag array; 2) a data array capable of storing a translated physical address corresponding to the untranslated address in one of N data entries in the data array; and 3) a region configuration array capable of storing region configuration bits associated with the translated physical address in one of N region configuration entries in the region configuration array.
摘要翻译：公开了在x86兼容处理器中使用的翻译后备缓冲器（TLB），其存储与存储在TLB中的每个物理地址相关联的区域配置位（或属性位），并使区域配置位可用于物理地址由TLB生成/翻译的同时。 TLB包括：1）能够在标签阵列中的N个标签条目之一中存储非翻译地址的标签阵列; 2）数据阵列，其能够将对应于未翻译地址的翻译物理地址存储在数据阵列中的N个数据条目之一中; 以及3）区域配置阵列，其能够在所述区域配置阵列中的N个区域配置条目之一中存储与所转换的物理地址相关联的区域配置位。

2. 发明授权

US5946718A Shadow translation look-aside buffer and method of operation 失效
标题翻译：阴影翻译后备缓冲区和操作方法
公开(公告)号：US5946718A
公开(公告)日：1999-08-31
申请号：US866441
申请日：1997-05-30
申请人： Daniel W. Green
发明人： Daniel W. Green
IPC分类号： G06F12/10
CPC分类号： G06F12/1027
摘要： For use in an x86-compatible processor having a physically-addressable cache and a primary translation look-aside buffer (primary TLB) that translates logical addresses into physical addresses for addressing the cache, a circuit and method for increasing a translation speed of the primary TLB and a computer system employing the circuit or the method. In one embodiment, the circuit includes a shadow TLB, located proximate the cache, that contains a copy of physical addresses stored in the primary TLB, the physical addresses retrievable from the shadow TLB thereby avoiding logic circuitry interposed between the primary TLB and the cache.
摘要翻译：为了在具有物理可寻址缓存的x86兼容处理器和用于将逻辑地址转换为用于寻址高速缓存的物理地址的主要翻译后备缓冲器（主TLB）中使用，用于提高主缓冲器的转换速度的电路和方法 TLB和采用该电路或方法的计算机系统。在一个实施例中，电路包括位于高速缓存附近的阴影TLB，其包含存储在主TLB中的物理地址的副本，该物理地址可从阴影TLB中检索，从而避免插入在主TLB和高速缓存之间的逻辑电路。

3. 发明授权

US06351789B1 Built-in self-test circuit and method for validating an associative data array 失效
标题翻译：内置自检电路和验证联想数据阵列的方法
公开(公告)号：US06351789B1
公开(公告)日：2002-02-26
申请号：US09086866
申请日：1998-05-29
申请人： Daniel W. Green
发明人： Daniel W. Green
IPC分类号： G06F1200
CPC分类号： G06F12/0802
摘要： There is disclosed, for use in a processing device having an N-way set associative data array (such as an L1 cache), a built-in self-test (BIST) circuit for testing the validity of storage locations in the data array. The BIST circuit comprises 1) a memory capable of storing a test program executable by the processing device, wherein the test program is capable of testing the validity of the storage locations in the data array; and 2) a controller capable of copying the test program from the memory into first selected storage locations in a first way in the data array, wherein the processing device executes the copied test program stored in the first selected storage locations subsequent to the copying to thereby test the validity of second selected storage locations in at least one of the N ways.
摘要翻译：公开了用于具有N路组相关数据阵列（例如L1高速缓存）的处理装置，用于测试数据阵列中的存储位置的有效性的内置自检（BIST）电路。 BIST电路包括：1）能够存储可由处理设备执行的测试程序的存储器，其中测试程序能够测试数据阵列中的存储位置的有效性; 以及2）能够以数据阵列中的第一种方式从所述存储器将所述测试程序复制到所述第一选定存储位置的控制器，其中，所述处理设备执行存储在所述复制之后的所述第一选定存储位置中的复制的测试程序，从而以N种方式中的至少一种测试第二选定存储位置的有效性。

4. 发明授权

US6065091A Translation look-aside buffer slice circuit and method of operation 失效
标题翻译：翻译后备缓冲片电路及其操作方法
公开(公告)号：US6065091A
公开(公告)日：2000-05-16
申请号：US866565
申请日：1997-05-30
申请人： Daniel W. Green
发明人： Daniel W. Green
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/1054
摘要： For use in an x-86 processor having a physically-addressable cache and an associated translation look-aside buffer (primary TLB) that stores corresponding logical and physical addresses for addressing the cache, a circuit for increasing a retrieval speed of a line from the cache. In one embodiment, the circuit comprises: 1) a TLB slice, located proximate the cache, that contains copies of portions of the physical addresses stored in the primary TLB and returns one of the portions as a function of a portion of a logical address supplied thereto; and 2) a decoder, coupled to the TLB slice, that decodes the one of the portions to yield multiplexer selection signals, the TLB slice and the decoder cooperating to increase the retrieval speed by avoiding logic circuitry interposed between the primary TLB and the cache.
摘要翻译：为了用于具有物理可寻址缓存的x-86处理器和用于存储用于寻址高速缓存的相应逻辑和物理地址的相关联的翻译后备缓冲器（主TLB），用于增加线路的检索速度的电路缓存。在一个实施例中，电路包括：1）位于高速缓存附近的TLB片，其包含存储在主TLB中的物理地址的部分的副本，并根据所提供的逻辑地址的一部分返回部分之一到; 以及2）耦合到TLB片的解码器，其解码所述部分中的一个以产生多路复用器选择信号，TLB片和解码器协作以通过避免插入在主TLB和高速缓存之间的逻辑电路来提高检索速度。

5. 发明授权

US6032241A Fast RAM for use in an address translation circuit and method of operation 失效
标题翻译：快速RAM用于地址转换电路和操作方法
公开(公告)号：US6032241A
公开(公告)日：2000-02-29
申请号：US992355
申请日：1997-12-17
申请人： Daniel W. Green
发明人： Daniel W. Green
IPC分类号： G06F12/10
CPC分类号： G06F12/1054
摘要： There is disclosed, for use in an x86-compatible processor having a physically-addressable cache, an address translation device for translating linear addresses received from a plurality of linear address sources and selectively accessing physical addresses, linear addresses, and controls signals stored in the address translation device. The address translation device comprises: 1) an array of data cells for storing the physical addresses, linear addresses, and controls signals in a plurality of entries; 2) an entry selection circuit for receiving a first linear address from a first linear address source and, in response thereto, generating an entry select output corresponding to the first linear address; 3) a first switch controllable by the entry select output; and 4) a second switch controllable by an address source select signal received from the first linear address source, wherein the entry select output and the address source select signal close the first and second switches to thereby form a connection path, the formation of the connection path causing a selected data cell to transfer a stored target bit stored therein to a data bit line of the address translation device.
摘要翻译：公开了用于具有物理可寻址缓存的x86兼容处理器中的地址转换装置，用于转换从多个线性地址源接收的线性地址并选择性地访问物理地址，线性地址和控制存储在地址转换设备。地址转换装置包括：1）用于存储多个条目中的物理地址，线性地址和控制信号的数据单元阵列; 2）一种入口选择电路，用于从第一线性地址源接收第一线性地址，并响应于此产生对应于第一线性地址的入口选择输出; 3）由入口选择输出控制的第一开关; 以及4）由从所述第一线性地址源接收的地址源选择信号控制的第二开关，其中所述入口选择输出和所述地址源选择信号使所述第一和第二开关闭合从而形成连接路径，形成所述连接使所选择的数据单元将存储的存储的目标位传送到地址转换装置的数据位线的路径。

6. 发明授权

US5940858A Cache circuit with programmable sizing and method of operation 失效
标题翻译：具有可编程尺寸和操作方法的缓存电路
公开(公告)号：US5940858A
公开(公告)日：1999-08-17
申请号：US865664
申请日：1997-05-30
申请人： Daniel W. Green
发明人： Daniel W. Green
IPC分类号： G06F12/08
CPC分类号： G06F12/0893 , G06F12/0864 , G06F2212/601
摘要： For use in an x86-compatible processor having a cache, a circuit and method for setting a size of the cache and a computer system employing the circuit or the method. In one embodiment, the circuit includes: (1) multiple access circuitry dividing the cache into separate physically-addressable sectors and (2) sector disabling circuitry, coupled to the cache, that selectively allows at least one of the sectors to be disabled to decrease the size of the cache.
摘要翻译：用于具有高速缓存的x86兼容处理器，用于设置高速缓存大小的电路和方法以及采用该电路或该方法的计算机系统。在一个实施例中，电路包括：（1）将高速缓存划分为不同的可物理寻址的扇区的多址接入电路和（2）耦合到高速缓存的扇区禁用电路，其选择性地允许至少一个扇区被禁用以减少缓存的大小。

7. 发明授权

US07785326B2 System for intramedullary rod fixation and method therefor 有权
标题翻译：髓内钉固定系统及其方法
公开(公告)号：US07785326B2
公开(公告)日：2010-08-31
申请号：US11250498
申请日：2005-10-14
申请人： Daniel W. Green , Joseph L. Molino
发明人： Daniel W. Green , Joseph L. Molino
IPC分类号： A61B17/56
CPC分类号： A61B17/72 , A61B17/1717 , A61B17/725 , A61B17/7291 , A61B17/8605 , A61B17/8625 , A61B17/8685
摘要： A system and method for securing an intramedullary rod in a medullary canal of a long bone is provided. The system includes an intramedullary rod and a screw assembly for receiving the rod. The screw assembly has a transverse receiving bore for receiving the intramedullary rod and a securing member movable toward the bore for securing the rod to the screw assembly. An alignment jig may also be provided for aligning the rod with the receiving bore during installation.
摘要翻译：提供了一种用于将髓内杆固定在长骨的髓质管中的系统和方法。该系统包括髓内杆和用于接收杆的螺钉组件。螺钉组件具有用于接收髓内杆的横向容纳孔和可朝向孔移动的固定构件，用于将杆固定到螺钉组件。还可以设置对准夹具，用于在安装期间将杆与接收孔对准。

8. 发明申请

US20100004652A1 Orthopedic method for correcting angular bone deformity 有权
标题翻译：骨矫正矫正方法矫正角骨畸形
公开(公告)号：US20100004652A1
公开(公告)日：2010-01-07
申请号：US12583515
申请日：2009-08-21
申请人： Daniel W. Green , Joseph L. Molino
发明人： Daniel W. Green , Joseph L. Molino
IPC分类号： A61B17/80 , A61B17/88
CPC分类号： A61B17/80 , A61B17/8004
摘要： An orthopedic device and method for correcting angular deformation of a bone structure having a growth plate. The device includes first and second hinge members connected together at a hinge joint. The device is adapted for mounting the orthopedic device to the bone structure with the pivot joint positioned over the growth plate. Alignment of the pivot joint with the growth plate promotes asymmetric growth of the growth plate to thereby correct the angular deformation.
摘要翻译：一种用于校正具有生长板的骨结构的角变形的矫形装置和方法。该装置包括在铰链接头处连接在一起的第一和第二铰链构件。该装置适于将骨科装置安装到骨骼结构上，而枢转关节位于生长板上方。枢轴关节与生长板的对准促进生长板的不对称生长，从而校正角变形。

9. 发明授权

US06405232B1 Leading bit prediction with in-parallel correction 有权
标题翻译：带并行校正的前端位预测
公开(公告)号：US06405232B1
公开(公告)日：2002-06-11
申请号：US09377139
申请日：1999-08-19
申请人： Daniel W. Green , Atul Dhablania , Jeffrey A. Lohman , Bang Nguyen
发明人： Daniel W. Green , Atul Dhablania , Jeffrey A. Lohman , Bang Nguyen
IPC分类号： G06F9302
CPC分类号： G06F7/74 , G06F5/012 , G06F7/485
摘要： For use in a processor having a floating point unit (FPU) capable of managing denormalized numbers in floating point notation, logic circuitry for, and a method of adding or subtracting two floating point numbers. In one embodiment, the logic circuitry includes: (1) an adder that receives the two floating point numbers and, based on a received instruction, adds or subtracts the two floating point numbers to yield a denormal sum or difference thereof, (2) a leading bit predictor that receives the two floating point numbers and performs logic operations thereon to yield predictive shift data denoting an extent to which the denormal sum or difference is required to be shifted to normalize the denormal sum or difference, the predictive shift data subject to being erroneous and (3) predictor corrector logic that receives the two floating point numbers and performs logic operations thereon to yield shift compensation data denoting an extent to which the predictive shift is erroneous. The denormal sum or difference, predictive shift data and shift compensation data are providable to a shifter to allow the denormal sum or difference to be normalized.
摘要翻译：用于具有能够管理浮点符号的非规范化数字的浮点单元（FPU）的处理器，用于加上或减去两个浮点数的逻辑电路和方法。在一个实施例中，逻辑电路包括：（1）接收两个浮点数的加法器，并且基于接收到的指令，加或减两个浮点数以产生其异常和或差，（2）a 接收两个浮点数并执行其上的逻辑运算的前导位预测器产生预测移位数据，该预测移位数据表示需要将非正交求和或差异移位到正规化异常和/ 错误和（3）预测器校正器逻辑，其接收两个浮点数并执行其上的逻辑运算以产生表示预测偏移错误程度的移位补偿数据。可以向移位器提供反正态和或差，预测移位数据和移位补偿数据，以允许正则化的归一化或不均匀。

10. 发明授权

US08029507B2 Orthopedic method for correcting angular bone deformity 有权
标题翻译：骨矫正矫正方法矫正角骨畸形
公开(公告)号：US08029507B2
公开(公告)日：2011-10-04
申请号：US12583515
申请日：2009-08-21
申请人： Daniel W. Green , Joseph L. Molino
发明人： Daniel W. Green , Joseph L. Molino
IPC分类号： A61B17/56 , A61B17/58 , A61B17/80 , A61B17/30
CPC分类号： A61B17/80 , A61B17/8004
摘要： An orthopedic device and method for correcting angular deformation of a bone structure having a growth plate. The device includes first and second hinge members connected together at a hinge joint. The device is adapted for mounting the orthopedic device to the bone structure with the pivot joint positioned over the growth plate. Alignment of the pivot joint with the growth plate promotes asymmetric growth of the growth plate to thereby correct the angular deformation.
摘要翻译：一种用于校正具有生长板的骨结构的角变形的矫形装置和方法。该装置包括在铰链接头处连接在一起的第一和第二铰链构件。该装置适于将骨科装置安装到骨骼结构上，而枢转关节位于生长板上方。枢轴关节与生长板的对准促进生长板的不对称生长，从而校正角变形。

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