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    • 3. 发明授权
    • Translation look-aside buffer for storing region configuration bits and method of operation
    • 用于存储区域配置位的翻译后备缓冲区和操作方法
    • US06351797B1
    • 2002-02-26
    • US09192122
    • 1998-11-13
    • Douglas R. Beard, Sr.Darren BensleyDaniel W. Green
    • Douglas R. Beard, Sr.Darren BensleyDaniel W. Green
    • G06F1210
    • G06F12/1027
    • There is disclosed, for use in an x86-compatible processor, a translation look-aside buffer (TLB) that stores region configuration bits (or attribute bits) associated with each physical address stored in the TLB and that makes the region configuration bits available at the same time that the physical address is generated/translated by the TLB. The TLB comprises: 1) a tag array capable of storing an untranslated address in one of N tag entries in the tag array; 2) a data array capable of storing a translated physical address corresponding to the untranslated address in one of N data entries in the data array; and 3) a region configuration array capable of storing region configuration bits associated with the translated physical address in one of N region configuration entries in the region configuration array.
    • 公开了在x86兼容处理器中使用的翻译后备缓冲器(TLB),其存储与存储在TLB中的每个物理地址相关联的区域配置位(或属性位),并使区域配置位可用于 物理地址由TLB生成/翻译的同时。 TLB包括:1)能够在标签阵列中的N个标签条目之一中存储非翻译地址的标签阵列; 2)数据阵列,其能够将对应于未翻译地址的翻译物理地址存储在数据阵列中的N个数据条目之一中; 以及3)区域配置阵列,其能够在所述区域配置阵列中的N个区域配置条目之一中存储与所转换的物理地址相关联的区域配置位。