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1. 发明授权

US08159040B2 Metal gate integration structure and method including metal fuse, anti-fuse and/or resistor 有权
标题翻译：金属栅极集成结构和方法，包括金属保险丝，反熔丝和/或电阻
公开(公告)号：US08159040B2
公开(公告)日：2012-04-17
申请号：US12119526
申请日：2008-05-13
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
IPC分类号： H01L29/00
CPC分类号： H01L27/0629 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.
摘要翻译：半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料栅电极。

2. 发明申请

US20090283840A1 METAL GATE INTEGRATION STRUCTURE AND METHOD INCLUDING METAL FUSE, ANTI-FUSE AND/OR RESISTOR 有权
标题翻译：金属栅组合结构和方法，包括金属保险丝，抗保险丝和/或电阻
公开(公告)号：US20090283840A1
公开(公告)日：2009-11-19
申请号：US12119526
申请日：2008-05-13
申请人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Ephrem G. Gebreselasie , Zhong-Xiang He , Herbert Lei Ho , Deok-kee Kim , Chandrasekharan Kothandaraman , Dan Moy , Robert Mark Rassel , John Matthew Safran , Kenneth Jay Stein , Norman Whitelaw Robson , Ping-Chuan Wang , Hongwen Yan
IPC分类号： H01L27/06 , H01L21/8234
CPC分类号： H01L27/0629 , H01L23/5252 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure and a method for fabricating the semiconductor structure provide a field effect device located and formed upon an active region of a semiconductor substrate and at least one of a fuse structure, an anti-fuse structure and a resistor structure located and formed at least in part simultaneously upon an isolation region laterally separated from the active region within the semiconductor substrate. The field effect device includes a gate dielectric comprising a high dielectric constant dielectric material and a gate electrode comprising a metal material. The at least one of the fuse structure, anti-fuse structure and resistor structure includes a pad dielectric comprising the same material as the gate dielectric, and optionally, also a fuse, anti-fuse or resistor that may comprise the same metal material as the gate electrode.
摘要翻译：半导体结构和半导体结构的制造方法提供一种场效应器件，其位于和形成在半导体衬底的有源区上，并且至少一个熔丝结构，抗熔丝结构和电阻结构中的至少一个至少位于并形成部分地同时地在与半导体衬底内的有源区域横向分离的隔离区域上。场效应器件包括包括高介电常数介电材料的栅极电介质和包括金属材料的栅电极。熔丝结构，反熔丝结构和电阻器结构中的至少一个包括包括与栅极电介质相同的材料的焊盘电介质，以及可选地还包括熔断器，反熔丝或电阻器，其可以包括与所述栅极电介质相同的金属材料栅电极。

3. 发明授权

US08907405B2 Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures 有权
标题翻译：具有双沟槽区域的半导体结构和制造半导体结构的方法
公开(公告)号：US08907405B2
公开(公告)日：2014-12-09
申请号：US13088663
申请日：2011-04-18
申请人： Reinaldo A. Vega , Hongwen Yan
发明人： Reinaldo A. Vega , Hongwen Yan
IPC分类号： H01L29/66 , H01L21/336 , H01L29/78 , H01L23/12 , H01L21/02
CPC分类号： H01L29/66628 , H01L21/02112 , H01L21/0226 , H01L23/12 , H01L29/6653 , H01L29/7834 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor structures with dual trench regions and methods of manufacturing the semiconductor structures are provided herein. The method includes forming a gate structure on an active region and high-k dielectric material formed in one or more trenches adjacent to the active region. The method further includes forming a sacrificial material over the active region and portions of the high-k dielectric material adjacent sidewalls of the active region. The method further includes removing unprotected portions of the high-k dielectric material, leaving behind a liner of high-k dielectric material on the sidewalls of the active region. The method further includes removing the sacrificial material and forming a raised source and drain region adjacent to sidewalls of the gate structure.
摘要翻译：本文提供具有双沟槽区域的半导体结构和制造半导体结构的方法。该方法包括在有源区上形成栅极结构，并形成在与有源区相邻的一个或多个沟槽中的高k电介质材料。该方法还包括在有源区域上形成牺牲材料，并且在有源区域的邻近侧壁的高k电介质材料的部分上形成牺牲材料。该方法还包括去除高k电介质材料的未受保护的部分，在有源区的侧壁上留下高k电介质材料的衬垫。该方法还包括去除牺牲材料并形成与栅极结构的侧壁相邻的凸起的源极和漏极区域。

4. 发明申请

US20120142181A1 CMOS STRUCTURE AND METHOD FOR FABRICATION THEREOF USING MULTIPLE CRYSTALLOGRAPHIC ORIENTATIONS AND GATE MATERIALS 失效
标题翻译： CMOS结构及其使用多种晶体取向和栅极材料制造的方法
公开(公告)号：US20120142181A1
公开(公告)日：2012-06-07
申请号：US13369707
申请日：2012-02-09
申请人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/28
CPC分类号： H01L21/28079 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/6659
摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
摘要翻译：制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。平坦化层位于第二栅极材料层上。平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。也可以在第一栅极叠层上形成蚀刻停止层。所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

5. 发明授权

US08158481B2 CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials 有权
标题翻译： CMOS结构及其制造方法，使用多个晶体取向和栅极材料
公开(公告)号：US08158481B2
公开(公告)日：2012-04-17
申请号：US12683535
申请日：2010-01-07
申请人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh V. Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/8234
CPC分类号： H01L21/28079 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/6659
摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
摘要翻译：制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。平坦化层位于第二栅极材料层上。平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。也可以在第一栅极叠层上形成蚀刻停止层。所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

6. 发明申请

US20090152651A1 GATE STACK STRUCTURE WITH OXYGEN GETTERING LAYER 审中-公开
标题翻译：具有氧气捕获层的门盖结构
公开(公告)号：US20090152651A1
公开(公告)日：2009-06-18
申请号：US11958595
申请日：2007-12-18
申请人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
发明人： Huiming Bu , Rick Carter , Michael P. Chudzik , Troy L. Graves , Michael A. Gribelyuk , Rashmi Jha , Vijay Narayanan , Dae-Gyu Park , Vamsi K. Paruchuri , Hongwen Yan , Bruce B. Doris , Keith Kwong Hon Wong
IPC分类号： H01L29/78
CPC分类号： H01L21/28088 , H01L29/4966 , H01L29/517
摘要： A transistor has a channel region in a substrate and source and drain regions in the substrate on opposite sides of the channel region. A gate stack is formed on the substrate above the channel region. This gate stack comprises an interface layer contacting the channel region of the substrate, and a high-k dielectric layer (having a dielectric constant above 4.0) contacting (on) the interface layer. A Nitrogen rich first metal Nitride layer contacts (is on) the dielectric layer, and a metal rich second metal Nitride layer contacts (is on) the first metal Nitride layer. Finally, a Polysilicon cap contacts (is on) the second metal Nitride layer.
摘要翻译：晶体管在衬底中具有通道区域，在沟道区域的相对侧上具有衬底中的源极和漏极区域。栅极堆叠形成在沟道区域上方的衬底上。该栅极堆叠包括与衬底的沟道区域接触的界面层和与界面层（上）接触的高k电介质层（介电常数高于4.0）。富氮的第一金属氮化物层在电介质层上接触，并且富金属的第二金属氮化物层与第一金属氮化物层接触（在）上。最后，多晶硅帽与第二金属氮化物层接触（在）上。

7. 发明申请

US20080224238A1 ADVANCED HIGH-k GATE STACK PATTERNING AND STRUCTURE CONTAINING A PATTERNED HIGH-k GATE STACK 有权
标题翻译：先进的高k栅格堆叠图案和结构包含一个图案高k门板堆叠
公开(公告)号：US20080224238A1
公开(公告)日：2008-09-18
申请号：US11685558
申请日：2007-03-13
申请人： Siva Kanakasabapathy , Ying Zhang , Edmund M. Sikorski , Hongwen Yan , Vijay Narayanan , Vamsi K. Paruchuri , Bruce B. Doris
发明人： Siva Kanakasabapathy , Ying Zhang , Edmund M. Sikorski , Hongwen Yan , Vijay Narayanan , Vamsi K. Paruchuri , Bruce B. Doris
IPC分类号： H01L29/76 , H01L21/302
CPC分类号： H01L21/31111 , H01L21/28088 , H01L21/31144 , H01L21/31645 , H01L21/823807 , H01L21/823828 , H01L29/045 , H01L29/4966 , H01L29/513 , H01L29/517
摘要： An advanced method of patterning a gate stack including a high-k gate dielectric that is capped with a high-k gate dielectric capping layer such as, for example, a rare earth metal (or rare earth like)-containing layer is provided. In particular, the present invention provides a method in which a combination of wet and dry etching is used in patterning such gate stacks which substantially reduces the amount of remnant high-k gate dielectric capping material remaining on the surface of a semiconductor substrate to a value that is less than 1010 atoms/cm2, preferably less than about 109 atoms/cm2.
摘要翻译：提供了一种构图栅极堆叠的先进方法，该栅极堆叠包括用例如含有稀土金属（或稀土类））层的高k栅介质覆盖层封盖的高k栅极电介质。特别地，本发明提供了一种方法，其中使用湿蚀刻和干蚀刻的组合来构图这样的栅极堆叠，其将残留在半导体衬底的表面上的剩余的高k栅极电介质封盖材料的量基本上减小到值小于10 10原子/ cm 2，优选小于约10 9原子/ cm 2。

8. 发明申请

US20080194112A1 METHOD AND SYSTEM FOR PLASMA ETCHING HAVING IMPROVED ACROSS-WAFER ETCH UNIFORMITY 审中-公开
标题翻译：等离子体蚀刻的方法和系统具有改进的跨越蚀刻均匀性
公开(公告)号：US20080194112A1
公开(公告)日：2008-08-14
申请号：US11673128
申请日：2007-02-09
申请人： Qingyun Yang , Joyce C. Liu , Hongwen Yan , Ying Zhang
发明人： Qingyun Yang , Joyce C. Liu , Hongwen Yan , Ying Zhang
IPC分类号： H01L21/3065
CPC分类号： H01L21/32136 , H01L21/32137 , H01L21/6708
摘要： A method for improving across-wafer etch uniformity of semiconductor devices in an etching chamber, wherein the method includes: introducing a first flow of gas mixtures from a central gas distribution plate manifold; introducing a second flow of gas mixtures from an auxiliary gas feed; and controlling process parameters including one or more of: duration, power, pressure, and gas flow rates for the first and second flow of gas mixtures; wherein the central gas distribution plate manifold is positioned above the semiconductor wafer; wherein the auxiliary gas feed is positioned around the perimeter of the semiconductor wafer; and wherein the controlling of the process parameters of the central gas distribution plate manifold and the auxiliary gas feed is facilitated by independent controls.
摘要翻译：一种用于改善蚀刻室中的半导体器件的跨晶片蚀刻均匀性的方法，其中所述方法包括：从中央气体分配板歧管引入第一气体混合物流; 从辅助气体进料引入第二气体混合物流; 以及控制过程参数，包括以下一个或多个：气体混合物的第一和第二流动的持续时间，功率，压力和气体流速; 其中所述中央气体分配板歧管位于所述半导体晶片的上方; 其中所述辅助气体进料围绕所述半导体晶片的周边定位; 并且其中通过独立控制来促进对中央气体分配板歧管和辅助气体进料的工艺参数的控制。

9. 发明授权

US07329602B2 Wiring structure for integrated circuit with reduced intralevel capacitance 有权
标题翻译：具有降低的体积电容的集成电路的接线结构
公开(公告)号：US07329602B2
公开(公告)日：2008-02-12
申请号：US11203944
申请日：2005-08-15
申请人： Richard S. Wise , Bomy A. Chen , Mark C. Hakey , Hongwen Yan
发明人： Richard S. Wise , Bomy A. Chen , Mark C. Hakey , Hongwen Yan
IPC分类号： H01L21/4763
CPC分类号： H01L23/5222 , H01L21/7682 , H01L23/53295 , H01L2221/1057 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.
摘要翻译：形成用于集成电路的布线结构的方法包括以下步骤：在介电材料层中形成多个特征，以及在特征的侧壁上形成间隔物。然后在特征中形成导体，通过间隔件与侧壁分离。然后去除间隔物，在侧壁处形成气隙，使得导体通过气隙与侧壁分离。导体之上和之下的介电层可以是具有比导体之间的电介质的介电常数小的介电常数的低k电介质。每个导体的横截面具有与低k电介质层接触的底部，与另一低k电介质接触的顶部和仅与气隙接触的侧面。气隙用于降低电容值。

10. 发明申请

US20070278586A1 CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials 失效
标题翻译： CMOS结构及其制造方法，使用多个晶体取向和栅极材料
公开(公告)号：US20070278586A1
公开(公告)日：2007-12-06
申请号：US11444011
申请日：2006-05-31
申请人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
发明人： Tze-Chiang Chen , Meikei Ieong , Rajarao Jammy , Mukesh Khare , Chun-yung Sung , Richard Wise , Hongwen Yan , Ying Zhang
IPC分类号： H01L29/94
CPC分类号： H01L21/28079 , H01L21/823807 , H01L21/823842 , H01L21/823878 , H01L21/84 , H01L27/1203 , H01L29/045 , H01L29/6659
摘要： Methods for fabricating a CMOS structure use a first gate stack located over a first orientation region of a semiconductor substrate. A second gate material layer is located over the first gate stack and a laterally adjacent second orientation region of the semiconductor substrate. A planarizing layer is located upon the second gate material layer. The planarizing layer and the second gate material layer are non-selectively etched to form a second gate stack that approximates the height of the first gate stack. An etch stop layer may also be formed upon the first gate stack. The resulting CMOS structure may comprise different gate dielectrics, metal gates and silicon gates.
摘要翻译：制造CMOS结构的方法使用位于半导体衬底的第一取向区域上方的第一栅极堆叠。第二栅极材料层位于第一栅极叠层上方和半导体衬底的横向相邻的第二取向区域上。平坦化层位于第二栅极材料层上。平面化层和第二栅极材料层被非选择性蚀刻以形成近似第一栅极堆叠的高度的第二栅极堆叠。也可以在第一栅极叠层上形成蚀刻停止层。所得到的CMOS结构可以包括不同的栅极电介质，金属栅极和硅栅极。

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