专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20130328174A1 Edge Protection of Bonded Wafers During Wafer Thinning 有权
标题翻译：晶圆薄化期间粘合晶片的边缘保护
公开(公告)号：US20130328174A1
公开(公告)日：2013-12-12
申请号：US13489861
申请日：2012-06-06
申请人： Douglas C. La Tulipe, JR. , Spyridon Skordas , Tuan A. Vo , Kevin R. Winstel
发明人： Douglas C. La Tulipe, JR. , Spyridon Skordas , Tuan A. Vo , Kevin R. Winstel
IPC分类号： H01L23/58 , H01L21/30
CPC分类号： H01L25/50 , H01L23/562 , H01L25/0657 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： A method of edge protecting bonded semiconductor wafers. A second semiconductor wafer and a first semiconductor wafer are attached by a bonding layer/interface and the second semiconductor wafer undergoes a thinning process. As a part of the thinning process, a first protective layer is applied to the edges of the second and first semiconductor wafers. A third semiconductor wafer is attached to the second semiconductor wafer by a bonding layer/interface and the third semiconductor wafer undergoes a thinning process. As a part of the thinning process, a second protective layer is applied to the edges of the third semiconductor wafer and over the first protective layer. The first, second and third semiconductor wafers form a wafer stack. The wafer stack is diced into a plurality of 3D chips while maintaining the first and second protective layers.
摘要翻译：边缘保护键合半导体晶片的方法。第二半导体晶片和第一半导体晶片通过接合层/界面附着，并且第二半导体晶片进行变薄处理。作为稀化过程的一部分，第一保护层被施加到第二和第一半导体晶片的边缘。第三半导体晶片通过接合层/界面附接到第二半导体晶片，并且第三半导体晶片经历变薄处理。作为稀化过程的一部分，第二保护层被施加到第三半导体晶片的边缘并且在第一保护层上。第一，第二和第三半导体晶片形成晶片叠层。晶片堆叠被切成多个3D芯片，同时保持第一和第二保护层。

2. 发明申请

US20120037962A1 SEMICONDUCTOR STRUCTURE HAVING A CONTACT-LEVEL AIR GAP WITHIN THE INTERLAYER DIELECTRICS ABOVE A SEMICONDUCTOR DEVICE AND A METHOD OF FORMING THE SEMICONDUCTOR STRUCTURE USING A SELF-ASSEMBLY APPROACH 有权
标题翻译：在半导体器件之前的中间层电介质中具有接触层空气隙的半导体结构和使用自组装方法形成半导体结构的方法
公开(公告)号：US20120037962A1
公开(公告)日：2012-02-16
申请号：US12854352
申请日：2010-08-11
申请人： Gregory Breyta , David V. Horak , Elbert E. Huang , Charles W. Koburger, III , Douglas C. La Tulipe, JR. , Shom Ponoth
发明人： Gregory Breyta , David V. Horak , Elbert E. Huang , Charles W. Koburger, III , Douglas C. La Tulipe, JR. , Shom Ponoth
IPC分类号： H01L23/48 , H01L21/768 , H01L29/78
CPC分类号： H01L21/7682 , H01L21/31144 , H01L23/4821 , H01L23/485 , H01L23/5222 , H01L23/5329 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： Disclosed are embodiments of a semiconductor structure having a contact-level air gap within the interlayer dielectrics above a semiconductor device in order to minimize parasitic capacitances (e.g., contact-to-contact capacitance, contact-to-diffusion region capacitance, gate-to-contact capacitance, gate-to-diffusion region capacitance, etc.). Specifically, the structure can comprise a semiconductor device on a substrate and at least three dielectric layers stacked above the semiconductor device. An air gap is positioned with the second dielectric layer aligned above the semiconductor device and extending vertically from the first dielectric layer to the third dielectric layer. Also disclosed are embodiments of a method of forming such a semiconductor structure using a self-assembly approach.
摘要翻译：公开了在半导体器件之上的层间电介质中具有接触电平空气间隙的半导体结构的实施例，以便最小化寄生电容（例如，接触 - 接触电容，接触 - 扩散区电容，栅 - 接触电容，栅极到扩散区域电容等）。具体地，该结构可以包括在衬底上的半导体器件和堆叠在半导体器件上方的至少三个电介质层。定位气隙，其中第二电介质层在半导体器件上方对齐并从第一介电层垂直延伸到第三介质层。还公开了使用自组装方法形成这种半导体结构的方法的实施例。

3. 发明申请

US20120104512A1 SEALED AIR GAP FOR SEMICONDUCTOR CHIP 有权
标题翻译：密封用于半导体芯片的空气隙
公开(公告)号：US20120104512A1
公开(公告)日：2012-05-03
申请号：US12914132
申请日：2010-10-28
申请人： David V. Horak , Elbert E. Huang , Charles W. Koburger, III , Douglas C. La Tulipe, JR. , Shom Ponoth
发明人： David V. Horak , Elbert E. Huang , Charles W. Koburger, III , Douglas C. La Tulipe, JR. , Shom Ponoth
IPC分类号： H01L27/088 , H01L21/28 , H01L21/336
CPC分类号： H01L29/4991 , H01L21/823468 , H01L29/401 , H01L29/4983 , H01L29/6653 , H01L29/66545
摘要： A semiconductor chip including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a contact contacting a portion of the gate and a portion of the sidewall; and a sealed air gap between the sidewall, the dielectric layer and the contact.
摘要翻译：一种包括衬底的半导体芯片; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 接触所述门的一部分和所述侧壁的一部分的接触; 以及侧壁，介电层和接触件之间的密封气隙。

4. 发明申请

US20110097870A1 METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS 有权
公开(公告)号：US20110097870A1
公开(公告)日：2011-04-28
申请号：US12540457
申请日：2009-08-13
申请人： Douglas C. La Tulipe, JR. , Mark Todhunter Robson
发明人： Douglas C. La Tulipe, JR. , Mark Todhunter Robson
IPC分类号： H01L21/8234
CPC分类号： H01L27/0688 , H01L21/76804 , H01L21/76898 , H01L23/481 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

5. 发明申请

US20100133616A1 METHODS OF FORMING WIRING TO TRANSISTOR AND RELATED TRANSISTOR 审中-公开
标题翻译：形成晶体管和相关晶体管的方法
公开(公告)号：US20100133616A1
公开(公告)日：2010-06-03
申请号：US12701685
申请日：2010-02-08
申请人： David J. Frank , Douglas C. La Tulipe, JR. , Steven E. Steen , Anna W. Topol
发明人： David J. Frank , Douglas C. La Tulipe, JR. , Steven E. Steen , Anna W. Topol
IPC分类号： H01L29/06
CPC分类号： H01L29/66477 , H01L21/76898 , H01L23/481 , H01L29/78 , H01L2924/0002 , H01L2924/00
摘要： Methods of wiring to a transistor and a related transistor are disclosed. In one embodiment, the method includes a method of forming wiring to a transistor, the method comprising: forming a transistor on a semiconductor-on-insulator (SOI) substrate using masks that are mirror images of an intended layout, the forming including forming a gate and a source/drain region for each and a channel, the SOI substrate including a semiconductor-on-insulator (SOI) layer, a buried insulator layer and a silicon substrate; forming a dielectric layer over the transistor; bonding the dielectric layer to another substrate; removing the silicon substrate from the SOI substrate to the buried insulator layer; forming a contact to each of the source/drain region and the gate from a channel side of the gate; and forming at least one wiring to the contacts on the channel side of the gate.
摘要翻译：公开了向晶体管和相关晶体管布线的方法。在一个实施例中，该方法包括一种向晶体管形成布线的方法，所述方法包括：使用作为预期布局的镜像的掩模在绝缘体上半导体（SOI）衬底上形成晶体管，所述形成包括形成栅极和源极/漏极区域，所述SOI衬底包括绝缘体上半导体（SOI）层，掩埋绝缘体层和硅衬底; 在所述晶体管上形成介电层; 将介电层粘合到另一基底上; 将硅衬底从SOI衬底移除到掩埋绝缘体层; 从栅极的沟道侧形成与源极/漏极区域和栅极中的每一个的接触; 以及形成至少一条布线到栅极通道侧上的触点。

6. 发明申请

US20090065941A1 METHOD OF FABRICATING ULTRA-DEEP VIAS AND THREE-DIMENSIONAL INTEGRATED CIRCUITS USING ULTRA-DEEP VIAS 有权
公开(公告)号：US20090065941A1
公开(公告)日：2009-03-12
申请号：US11853118
申请日：2007-09-11
申请人： Douglas C. La Tulipe, JR. , Mark Todhunter Robson
发明人： Douglas C. La Tulipe, JR. , Mark Todhunter Robson
IPC分类号： H01L23/48
CPC分类号： H01L21/76802 , H01L21/76804 , H01L27/0688 , H01L2224/80896 , H01L2224/9202
摘要： A method of forming a high aspect ratio via opening through multiple dielectric layers, a high aspect ratio electrically conductive via, methods of forming three-dimension integrated circuits, and three-dimensional integrated circuits. The methods include forming a stack of at least four dielectric layers and etching the first and third dielectric layers with processes selective to the second and fourth dielectric layers, etching the second and third dielectric layers with processes selective to the first and second dielectric layers. Advantageously the process used to etch the third dielectric layer is not substantially selective to the first dielectric layer.

7. 发明申请

US20140008731A1 FIELD-EFFECT-TRANSISTOR WITH SELF-ALIGNED DIFFUSION CONTACT 有权
标题翻译：具有自对准扩散接触的场效应晶体管
公开(公告)号：US20140008731A1
公开(公告)日：2014-01-09
申请号：US13542003
申请日：2012-07-05
申请人： Charles William Koburger, III , Douglas C. La Tulipe, JR.
发明人： Charles William Koburger, III , Douglas C. La Tulipe, JR.
IPC分类号： H01L27/088 , H01L21/20
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66545 , H01L29/66795
摘要： Embodiments of the present invention provide a method of forming fin-type transistors having replace-gate electrodes with self-aligned diffusion contacts. The method includes forming one or more silicon fins on top of an oxide layer, the oxide layer being situated on top of a silicon donor wafer; forming one or more dummy gate electrodes crossing the one or more silicon fins; forming sidewall spacers next to sidewalls of the one or more dummy gate electrodes; removing one or more areas of the oxide layer thereby creating openings therein, the openings being self-aligned to edges of the one or more fins and edges of the sidewall spacers; forming an epitaxial silicon layer in the openings; removing the donor wafer; and siliciding at least a bottom portion of the epitaxial silicon layer. A semiconductor structure formed thereby is also provided.
摘要翻译：本发明的实施例提供了一种形成具有具有自对准扩散接触的替代栅电极的鳍式晶体管的方法。该方法包括在氧化物层的顶部上形成一个或多个硅散热片，氧化物层位于硅供体晶片的顶部; 形成与所述一个或多个硅散热片交叉的一个或多个虚拟栅电极; 在所述一个或多个虚拟栅电极的侧壁旁边形成侧壁间隔物; 去除所述氧化物层的一个或多个区域，从而在其中形成开口，所述开口与所述侧壁间隔物的所述一个或多个翅片和边缘的边缘自对准; 在所述开口中形成外延硅层; 去除施主晶片; 并且至少硅化外延硅层的底部。还提供了由此形成的半导体结构。

8. 发明申请

US20130299897A1 INVERTED THIN CHANNEL MOSFET WITH SELF-ALIGNED EXPANDED SOURCE/DRAIN 有权
公开(公告)号：US20130299897A1
公开(公告)日：2013-11-14
申请号：US13468313
申请日：2012-05-10
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, JR.
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, JR.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/743 , H01L21/76898 , H01L23/485 , H01L27/12 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least with a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is thinned, and remaining portions of the bottom semiconductor layer are removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. A contact level dielectric layer is deposited on surfaces of the source and drain regions that are distal from the gate electrode, and contact vias are formed through the contact level dielectric layer.

9. 发明申请

US20120302019A1 NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES 失效
标题翻译： CMOS器件中固体源扩展区非松弛嵌入式压电器
公开(公告)号：US20120302019A1
公开(公告)日：2012-11-29
申请号：US13115314
申请日：2011-05-25
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, JR.
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, JR.
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.
摘要翻译：形成场效应晶体管（FET）器件的方法包括在衬底上形成图案化栅极结构; 在所述衬底上形成固体源掺杂剂材料，所述栅极结构的相邻侧壁间隔物; 在足以使来自固体源掺杂剂材料的掺杂剂在栅极结构下方的衬底内扩散并形成源极/漏极延伸区域的温度下进行退火工艺; 在形成源极/漏极延伸区之后，在与衬底相邻的衬底中形成相应于源极/漏极区的沟槽; 以及在所述沟槽中形成嵌入式半导体材料，以在所述栅极结构下面限定的所述衬底的沟道区域上产生应力。

10. 发明申请

US20120199886A1 SEALED AIR GAP FOR SEMICONDUCTOR CHIP 审中-公开
标题翻译：密封用于半导体芯片的空气隙
公开(公告)号：US20120199886A1
公开(公告)日：2012-08-09
申请号：US13020107
申请日：2011-02-03
申请人： David V. Horak , Elbert E. Huang , Charles W. Koburger, III , Douglas C. La Tulipe, JR. , Shom Ponoth
发明人： David V. Horak , Elbert E. Huang , Charles W. Koburger, III , Douglas C. La Tulipe, JR. , Shom Ponoth
IPC分类号： H01L29/772 , H01L21/336
CPC分类号： H01L29/4991 , H01L21/7682 , H01L21/76897 , H01L29/4983 , H01L29/6653 , H01L29/7833
摘要： A semiconductor chip, including a substrate; a dielectric layer over the substrate; a gate within the dielectric layer, the gate including a sidewall; a source and a drain in the substrate adjacent to the gate; a tapered contact contacting a portion of one of the source or the drain; and a sealed air gap between the sidewall and the contact.
摘要翻译：一种半导体芯片，包括基板; 介电层; 所述电介质层内的栅极，所述栅极包括侧壁; 邻近栅极的衬底中的源极和漏极; 与所述源极或所述漏极中的一个的一部分接触的锥形接触; 以及侧壁和接触件之间的密封气隙。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式