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1. 发明授权

US08592270B2 Non-relaxed embedded stressors with solid source extension regions in CMOS devices 失效
标题翻译： CMOS器件中具有固态源延伸区域的非轻松嵌入式应力源
公开(公告)号：US08592270B2
公开(公告)日：2013-11-26
申请号：US13115314
申请日：2011-05-25
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, Jr.
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, Jr.
IPC分类号： H01L21/336 , H01L21/8238
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.
摘要翻译：形成场效应晶体管（FET）器件的方法包括在衬底上形成图案化栅极结构; 在所述衬底上形成固体源掺杂剂材料，所述栅极结构的相邻侧壁间隔物; 在足以使来自固体源掺杂剂材料的掺杂剂在栅极结构下方的衬底内扩散并形成源极/漏极延伸区域的温度下进行退火工艺; 在形成源极/漏极延伸区之后，在与衬底相邻的衬底中形成相应于源极/漏极区的沟槽; 以及在所述沟槽中形成嵌入式半导体材料，以在所述栅极结构下面限定的所述衬底的沟道区域上产生应力。

2. 发明申请

US20130299897A1 INVERTED THIN CHANNEL MOSFET WITH SELF-ALIGNED EXPANDED SOURCE/DRAIN 有权
公开(公告)号：US20130299897A1
公开(公告)日：2013-11-14
申请号：US13468313
申请日：2012-05-10
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, JR.
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, JR.
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/66477 , H01L21/743 , H01L21/76898 , H01L23/485 , H01L27/12 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least with a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is thinned, and remaining portions of the bottom semiconductor layer are removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. A contact level dielectric layer is deposited on surfaces of the source and drain regions that are distal from the gate electrode, and contact vias are formed through the contact level dielectric layer.

3. 发明申请

US20120302019A1 NON-RELAXED EMBEDDED STRESSORS WITH SOLID SOURCE EXTENSION REGIONS IN CMOS DEVICES 失效
标题翻译： CMOS器件中固体源扩展区非松弛嵌入式压电器
公开(公告)号：US20120302019A1
公开(公告)日：2012-11-29
申请号：US13115314
申请日：2011-05-25
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, JR.
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Douglas C. La Tulipe, JR.
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823814 , H01L21/823807
摘要： A method of forming a field effect transistor (FET) device includes forming a patterned gate structure over a substrate; forming a solid source dopant material on the substrate, adjacent sidewall spacers of the gate structure; performing an anneal process at a temperature sufficient to cause dopants from the solid source dopant material to diffuse within the substrate beneath the gate structure and form source/drain extension regions; following formation of the source/drain extension regions, forming trenches in the substrate adjacent the sidewall spacers, corresponding to source/drain regions; and forming an embedded semiconductor material in the trenches so as to provide a stress on a channel region of the substrate defined beneath the gate structure.
摘要翻译：形成场效应晶体管（FET）器件的方法包括在衬底上形成图案化栅极结构; 在所述衬底上形成固体源掺杂剂材料，所述栅极结构的相邻侧壁间隔物; 在足以使来自固体源掺杂剂材料的掺杂剂在栅极结构下方的衬底内扩散并形成源极/漏极延伸区域的温度下进行退火工艺; 在形成源极/漏极延伸区之后，在与衬底相邻的衬底中形成相应于源极/漏极区的沟槽; 以及在所述沟槽中形成嵌入式半导体材料，以在所述栅极结构下面限定的所述衬底的沟道区域上产生应力。

4. 发明授权

US09219129B2 Inverted thin channel mosfet with self-aligned expanded source/drain 有权
标题翻译：反向薄沟道MOSFET，具有自对准扩展源极/漏极
公开(公告)号：US09219129B2
公开(公告)日：2015-12-22
申请号：US13468313
申请日：2012-05-10
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, Jr.
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Douglas C. La Tulipe, Jr.
IPC分类号： H01L29/78 , H01L21/336 , H01L29/66 , H01L21/74 , H01L27/12
CPC分类号： H01L29/66477 , H01L21/743 , H01L21/76898 , H01L23/485 , H01L27/12 , H01L27/1203 , H01L29/66545 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： A semiconductor structure including expanded source/drain regions that extend in an opposite direction of a gate electrode is provided. The semiconductor structure includes a stack of a body-containing region and a buried insulator portion, a gate dielectric in contact with a surface of the body-containing region, a gate electrode in contact with the gate dielectric, and a source region and a drain region laterally spaced by, and in contact with, the stack. The semiconductor structure further includes a contact level dielectric layer deposited on surfaces of the source region, the drain region and the buried insulator portion.
摘要翻译：提供包括在栅电极的相反方向上延伸的扩展的源极/漏极区域的半导体结构。所述半导体结构包括：体内区域和掩埋绝缘体部分的堆叠体，与所述主体容纳区域的表面接触的栅极电介质，与所述栅极电介质接触的栅极电极，以及源极区域和漏极横向间隔开并与堆叠接触的区域。半导体结构还包括沉积在源极区域，漏极区域和埋入绝缘体部分的表面上的接触电介质层。

5. 发明授权

US09054211B2 Compressively stressed FET device structures 有权
标题翻译：压应力FET器件结构
公开(公告)号：US09054211B2
公开(公告)日：2015-06-09
申请号：US13540801
申请日：2012-07-03
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Pranita Kulkarni , Ghavam G. Shahidi
IPC分类号： H01L27/088 , H01L21/8234 , H01L21/8238 , H01L29/66 , H01L29/78
CPC分类号： H01L21/823431 , H01L21/823412 , H01L21/823807 , H01L21/823821 , H01L29/66795 , H01L29/7843 , H01L29/7846 , H01L29/785
摘要： An FET device structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin. The Fin-FET device channel is compressively stressed due to the pressure on the fin. A further FET device structure has Fin-FET devices in a row. An oxide element extending perpendicularly to the row of fins is abutting the fins and exerts pressure onto the fins. Device channels of the Fin-FET devices are compressively stressed due to the pressure on the fins.
摘要翻译： FET器件结构具有具有Si基材料的翅片的Fin-FET器件。氧化物元件邻接翅片并对翅片施加压力。 Fin-FET器件通道由于鳍上的压力而受到压缩应力。另外的FET器件结构具有Fin-FET器件。垂直于翅片排延伸的氧化物元件邻接散热片并对翅片施加压力。 Fin-FET器件的器件通道由于鳍片上的压力而受到压缩应力。

6. 发明授权

US08994085B2 Integrated circuit including DRAM and SRAM/logic 有权
标题翻译：集成电路包括DRAM和SRAM /逻辑
公开(公告)号：US08994085B2
公开(公告)日：2015-03-31
申请号：US13551714
申请日：2012-07-18
申请人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
发明人： Veeraraghavan S. Basker , Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni , Tenko Yamashita , Chun-Chen Yeh
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119 , H01L21/84 , H01L27/11 , H01L27/12
CPC分类号： H01L21/84 , H01L27/10861 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L27/1108 , H01L27/1116 , H01L27/1203 , H01L29/945
摘要： An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.
摘要翻译：一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。

7. 发明授权

US08653596B2 Integrated circuit including DRAM and SRAM/logic 有权
标题翻译：集成电路包括DRAM和SRAM /逻辑
公开(公告)号：US08653596B2
公开(公告)日：2014-02-18
申请号：US13344885
申请日：2012-01-06
申请人： Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni
发明人： Kangguo Cheng , Bruce B. Doris , Terence B. Hook , Ali Khakifirooz , Pranita Kulkarni
IPC分类号： H01L21/70 , H01L27/12 , H01L21/762 , H01L21/84
CPC分类号： H01L29/945 , H01L21/84 , H01L27/1052 , H01L27/1087 , H01L27/10873 , H01L27/10894 , H01L27/1116 , H01L27/1203 , H01L27/1207
摘要： An integrated circuit includes an SOI substrate with a unitary N+ layer below the BOX, a P region in the N+ layer, an eDRAM with an N+ plate, and logic/SRAM devices above the P region. The P region functions as a back gate of the logic/SRAM devices. An optional intrinsic (undoped) layer can be formed between the P back gate layer and the N+ layer to reduce the junction field and lower the junction leakage between the P back gate and the N+ layer. In another embodiment an N or N+ back gate can be formed in the P region. The N+ back gate functions as a second back gate of the logic/SRAM devices. The N+ plate of the SOI eDRAM, the P back gate, and the N+ back gate can be electrically biased at the same or different voltage potentials. Methods to fabricate the integrated circuits are also disclosed.
摘要翻译：集成电路包括在BOX下方具有单一N +层的SOI衬底，N +层中的P区，N +板的eDRAM和P区上方的逻辑/ SRAM器件。 P区域用作逻辑/ SRAM器件的后门。可以在P背栅层和N +层之间形成可选的本征（未掺杂）层，以减少结场并降低P背栅与N +层之间的结泄漏。在另一个实施例中，可以在P区中形成N或N +背栅。 N +后门作为逻辑/ SRAM器件的第二个后门。 SOI eDRAM的N +板，P背栅极和N +背栅极可以在相同或不同的电压电位下被电偏置。还公开了制造集成电路的方法。

8. 发明申请

US20140024215A1 DOUBLE PATTERNING METHOD 有权
标题翻译：双重图案方法
公开(公告)号：US20140024215A1
公开(公告)日：2014-01-23
申请号：US13555306
申请日：2012-07-23
申请人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Ying Zhang
IPC分类号： B44C1/22 , H01B13/00 , H01L21/308
CPC分类号： H01L21/3086 , H01B13/00 , H01B19/04 , H01L21/0337 , H01L21/3081 , H01L21/32134 , H01L21/32137
摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.
摘要翻译：公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

9. 发明授权

US08629504B2 Extremely thin semiconductor-on-insulator (ETSOI) integrated circuit with on-chip resistors and method of forming the same 有权
标题翻译：具有片上电阻的非常薄的绝缘体上半导体（ETSOI）集成电路及其形成方法
公开(公告)号：US08629504B2
公开(公告)日：2014-01-14
申请号：US13433401
申请日：2012-03-29
申请人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi
发明人： Bruce B. Doris , Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi
IPC分类号： H01L21/00
CPC分类号： H01L27/1214 , H01L21/84 , H01L27/1203 , H01L27/13
摘要： An electrical device is provided that in one embodiment includes a semiconductor-on-insulator (SOI) substrate having a semiconductor layer with a thickness of less than 10 nm. A semiconductor device having a raised source region and a raised drain region of a single crystal semiconductor material of a first conductivity is present on a first surface of the semiconductor layer. A resistor composed of the single crystal semiconductor material of the first conductivity is present on a second surface of the semiconductor layer. A method of forming the aforementioned electrical device is also provided.
摘要翻译：提供了一种电气装置，其在一个实施例中包括具有厚度小于10nm的半导体层的绝缘体上半导体（SOI）基板。在半导体层的第一表面上存在具有第一导电性的单晶半导体材料的升高的源极区域和升高的漏极区域的半导体器件。由第一导电性的单晶半导体材料构成的电阻器存在于半导体层的第二表面上。还提供了形成上述电气装置的方法。

10. 发明申请

US20130344677A1 SHALLOW TRENCH ISOLATION STRUCTURES 有权
公开(公告)号：US20130344677A1
公开(公告)日：2013-12-26
申请号：US13531780
申请日：2012-06-25
申请人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
发明人： Bruce B. Doris , Kangguo Cheng , Balasubramanian S. Haran , Ali Khakifirooz , Pranita Kulkarni , Arvind Kumar , Shom Ponoth
IPC分类号： H01L21/762
CPC分类号： H01L29/0649 , H01L21/76224 , H01L21/76283
摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

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