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1. 发明授权

US07456420B2 Electrode for phase change memory device and method 有权
标题翻译：用于相变存储器件和方法的电极
公开(公告)号：US07456420B2
公开(公告)日：2008-11-25
申请号：US11308104
申请日：2006-03-07
申请人： Donna R. Cote , Ronald W. Mauthe , Keith Kwong Hon Wong
发明人： Donna R. Cote , Ronald W. Mauthe , Keith Kwong Hon Wong
IPC分类号： H01L47/00
CPC分类号： H01L45/06 , H01L27/2409 , H01L45/1233 , H01L45/1253 , H01L45/126 , H01L45/144 , H01L45/16 , H01L45/1641
摘要： An electrode for a memory material of a phase change memory device is disclosed. The electrode includes a first layer adhered to the memory material, the first layer including a nitride (ANx), where A is one of titanium (Ti) and tungsten (W) and x greater than zero, but is less than 1.0, and a second layer adhered to the first layer, the second layer including a nitride (ANy), where y is greater than or equal to 1.0. The multiple layer electrode allows the first layer to better adhere to chalcogenide based memory material, such as GST, than for example, stoichiometric TiN or WN, which prevents delamination. A phase change memory device and method are also disclosed.
摘要翻译：公开了一种用于相变存储器件的存储材料的电极。所述电极包括附着在所述记忆材料上的第一层，所述第一层包括氮化物（其中A是钛（Ti）和钨（W）中的一种，X大于零，但是小于1.0，第二层粘附到第一层，第二层包括氮化物（其中y大于或等于1.0）。多层电极允许第一层更好地粘附到基于硫族化物的记忆材料，例如GST，比例如化学计量的TiN或WN，其防止分层。还公开了相变存储器件和方法。

2. 发明授权

US6077786A Methods and apparatus for filling high aspect ratio structures with silicate glass 失效
标题翻译：用硅酸盐玻璃填充高纵横比结构的方法和装置
公开(公告)号：US6077786A
公开(公告)日：2000-06-20
申请号：US854011
申请日：1997-05-08
申请人： Ashima B. Chakravarti , Richard A. Conti , Donna R. Cote , Frank V. Liucci , Son V. Nguyen
发明人： Ashima B. Chakravarti , Richard A. Conti , Donna R. Cote , Frank V. Liucci , Son V. Nguyen
IPC分类号： H01L21/316 , H01L21/762 , H01L21/311
CPC分类号： H01L21/02274 , H01L21/02129 , H01L21/02131 , H01L21/02164 , H01L21/02271 , H01L21/31625 , H01L21/76224
摘要： Filling of narrow and/or high aspect ratio gaps and trenches with silicate glass is accomplished at reduced temperatures and without reflow by etching the glass concurrently with thermal chemical vapor deposition of the glass such that the deposition rate will exceed the etching rate by a relatively small net deposition rate near the surface with the excess deposition rate increasing over the depth of the trench or gap. The as-deposited glass film is made dense and stable by carrying out the concurrent etch and deposition process at an elevated temperature but which is within the maximum temperature and heat budget which can be tolerated by structures formed by previously performed processes. Fluorine can be incorporated in the silicate glass film as a dopant in sufficient concentration to reduce dielectric constant of the film. Phosphorus and/or boron can be incorporated into the film, as well, and may enhance void-free filling of trenches and gaps.
摘要翻译：使用硅酸盐玻璃填充窄和/或高长宽比的间隙和沟槽在降低的温度下完成，并且通过在玻璃的热化学气相沉积中同时蚀刻玻璃而不进行回流，使得沉积速率将超过蚀刻速率相对较小表面附近的净沉积速率随着沟槽或间隙的深度而增加。通过在升高的温度下进行同时蚀刻和沉积工艺，但是在由先前执行的工艺形成的结构可以容忍的最大温度和热量预算范围内，将沉积的玻璃膜制成致密和稳定的。氟可以以足够的浓度掺入到硅酸盐玻璃膜中作为掺杂剂以降低膜的介电常数。也可以将磷和/或硼掺入到膜中，并且可以增强沟槽和间隙的无空隙填充。

3. 发明授权

US06274440B1 Manufacturing of cavity fuses on gate conductor level 失效
标题翻译：在栅极导体级制造腔体保险丝
公开(公告)号：US06274440B1
公开(公告)日：2001-08-14
申请号：US09282134
申请日：1999-03-31
申请人： Kenneth C. Arndt , Axel C. Brintzinger , Richard A. Conti , Donna R. Cote , Chandrasekhar Narayan , Ravikumar Ramachandran , Thomas S. Rupp , Senthil K. Srinivasan
发明人： Kenneth C. Arndt , Axel C. Brintzinger , Richard A. Conti , Donna R. Cote , Chandrasekhar Narayan , Ravikumar Ramachandran , Thomas S. Rupp , Senthil K. Srinivasan
IPC分类号： H01L21336
CPC分类号： H01L23/5258 , H01L23/5256 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A structure and method for making a cavity fuse over a gate conductor stack. The method includes providing a semiconductor substrate having a gate conductor stack over a shallow trench isolation region, forming oxide layers on the substrate about the gate conductor stack, etching electrical contact holes through the oxide layers to the substrate, filling the electrical contact holes with a first conductive material to establish electrical contact with the gate conductor stack, etching a pattern in an uppermost oxide layer of the oxide layers, depositing a conductive layer of a second conductive material over the oxide layers and the electrical contacts, planarizing the conductive layer whereby the conductive material remains only in the pattern, anisotropically etching the oxide layers to form at least one etching hole through the oxide layers to the shallow trench isolation region, and isotropically etching at least a portion of the oxide layers about the etching hole, whereby a cavity is formed beneath at least a portion of the conductive layer pattern, the gate conductor stack comprising a fuse.
摘要翻译：用于在栅极导体堆叠上形成腔体熔断器的结构和方法。该方法包括提供在浅沟槽隔离区域上具有栅极导体堆叠的半导体衬底，在栅极导体堆叠周围形成衬底周围的氧化物层，蚀刻通过氧化物层到衬底的电接触孔，第一导电材料以与栅极导体堆叠建立电接触，蚀刻氧化物层的最上面的氧化物层中的图案，在氧化物层和电触点上沉积第二导电材料的导电层，平坦化导电层，由此导电材料仅保留在图案中，各向异性地蚀刻氧化物层以形成通过氧化物层到浅沟槽隔离区域的至少一个蚀刻孔，并且在蚀刻孔周围各向同性蚀刻至少一部分氧化层，形成在导电层图案的至少一部分之下，g 包括保险丝的导体堆叠。

4. 发明授权

US06252295B1 Adhesion of silicon carbide films 有权
标题翻译：碳化硅薄膜的粘附
公开(公告)号：US06252295B1
公开(公告)日：2001-06-26
申请号：US09597902
申请日：2000-06-19
申请人： Donna R. Cote , Daniel C. Edelstein , John A. Fitzsimmons , Thomas H. Ivers , Paul C. Jamison , Ernest Levine
发明人： Donna R. Cote , Daniel C. Edelstein , John A. Fitzsimmons , Thomas H. Ivers , Paul C. Jamison , Ernest Levine
IPC分类号： H01L2358
CPC分类号： H01L21/314 , C23C16/029 , C23C16/325 , H01L21/3145 , H01L21/31612 , H01L21/3185 , H01L21/76801 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要： The adhesion of a silicon carbide containing film to a surface is enhanced by employing a transition film of silicon nitride, silicon dioxide and/or silicon oxynitride.
摘要翻译：通过使用氮化硅，二氧化硅和/或氮氧化硅的过渡膜，增强了含碳化硅的膜对表面的粘合性。

5. 发明授权

US06798029B2 Method of fabricating micro-electromechanical switches on CMOS compatible substrates 有权
标题翻译：在CMOS兼容基板上制造微机电开关的方法
公开(公告)号：US06798029B2
公开(公告)日：2004-09-28
申请号：US10434999
申请日：2003-05-09
申请人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
发明人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L2982
CPC分类号： H01H59/0009 , H01H2059/0018 , H01H2059/0072
摘要： A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.
摘要翻译：描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。然后用牺牲脱模材料填充空腔。然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

6. 发明授权

US5216282A Self-aligned contact studs for semiconductor structures 失效
标题翻译：用于半导体结构的自对准接触器
公开(公告)号：US5216282A
公开(公告)日：1993-06-01
申请号：US784193
申请日：1991-10-29
申请人： Donna R. Cote , David Stanasolovich , Ronald A. Warren
发明人： Donna R. Cote , David Stanasolovich , Ronald A. Warren
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/336 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/522 , H01L29/78
CPC分类号： H01L23/5226 , H01L21/3105 , H01L21/76877 , H01L21/76879 , H01L21/76897 , H01L2924/0002
摘要： A contact stud for a semiconductor structure is fabricated by providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alignment structure, depositing an insulating layer contiguous with the sidewall spacer so as to insulate the semiconductor structure, etching the sidewall spacer selectively to the sidewall of the alignment structure, the semiconductor structure and the insulating layer for forming a contact window opening for allowing access to the semiconductor structure, and backfilling the contact window opening with a conductive material so as to contact the semiconductor structure for forming the stud.

7. 发明授权

US5187121A Process for fabrication of a semiconductor structure and contact stud 失效
标题翻译：用于制造半导体结构和接触柱的方法
公开(公告)号：US5187121A
公开(公告)日：1993-02-16
申请号：US810004
申请日：1991-12-18
申请人： Donna R. Cote , David Stanasolovich , Ronald A. Warren
发明人： Donna R. Cote , David Stanasolovich , Ronald A. Warren
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/311 , H01L21/318 , H01L21/768
CPC分类号： H01L21/76802 , H01L21/31051 , H01L21/31116 , H01L21/318 , H01L21/76885
摘要： Self-aligning process for fabricating a semiconductor structure and stud therefor on a semiconductor substrate comprises depositing a first material onto the substrate, depositing a second material onto the first material, removing excess portions of second material so as to form openings through the second material exposing excess portions of first material, whereby a selected portion of second material is retained and forms a sacrificial element, removing the excess portions of first material selectively to the substrate so as to extend the openings through the first material to the substrate, whereby a selected portion of first material is retained and forms the semiconductor structure, filling the openings with an insulating material, removing the sacrificial element selectively to the insulating material and the semiconductor structure for forming a contact window opening for allowing access to the semiconductor structure, and filling the contact window opening with stud material so as to contact the semiconductor structure for forming the stud.
摘要翻译：用于在半导体衬底上制造半导体结构和螺柱的自对准工艺包括将第一材料沉积到衬底上，将第二材料沉积到第一材料上，去除第二材料的多余部分，以便通过第二材料暴露第一材料的多余部分，由此保留第二材料的选定部分并形成牺牲元件，将第一材料的多余部分选择性地去除到衬底上，以将开口延伸穿过第一材料到衬底，由此选择部分的第一材料被保持并形成半导体结构，用绝缘材料填充开口，将牺牲元件选择性地去除绝缘材料和用于形成用于允许接近半导体结构的接触窗口的半导体结构，并且填充接触窗口打开与螺柱材料从而与形成螺柱的半导体结构接触。

8. 发明授权

US06635506B2 Method of fabricating micro-electromechanical switches on CMOS compatible substrates 有权
标题翻译：在CMOS兼容基板上制造微机电开关的方法
公开(公告)号：US06635506B2
公开(公告)日：2003-10-21
申请号：US10014660
申请日：2001-11-07
申请人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
发明人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L2100
CPC分类号： B81C1/00246 , B81B2201/016 , B81B2201/018 , B81B2203/0127 , B81B2207/07 , B81C1/00611 , B81C2201/0122 , B81C2203/0735 , H01G5/40 , H01H59/0009
摘要： A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.
摘要翻译：描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。然后用牺牲脱模材料填充空腔。然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

9. 发明授权

US5352927A Self-aligned contact studs for semiconductor structures 失效
标题翻译：用于半导体结构的自对准触头螺柱
公开(公告)号：US5352927A
公开(公告)日：1994-10-04
申请号：US968634
申请日：1992-10-29
申请人： Donna R. Cote , David Stanasolovich , Ronald A. Warren
发明人： Donna R. Cote , David Stanasolovich , Ronald A. Warren
IPC分类号： H01L21/28 , H01L21/3105 , H01L21/336 , H01L21/60 , H01L21/768 , H01L23/48 , H01L23/522 , H01L29/78 , H01L29/52 , H01L29/54
CPC分类号： H01L23/5226 , H01L21/3105 , H01L21/76877 , H01L21/76879 , H01L21/76897 , H01L2924/0002
摘要： A contact stud for a semiconductor structure is fabricated by providing a semiconductor substrate having an alignment structure, which includes a sidewall, and the semiconductor structure formed thereon, forming a sidewall spacer contiguous with the semiconductor structure and the sidewall of the alignment structure, depositing an insulating layer contiguous with the sidewall spacer so as to insulate the semiconductor structure, etching the sidewall spacer selectively to the sidewall of the alignment structure, the semiconductor structure and the insulating layer for forming a contact window opening for allowing access to the semiconductor structure, and backfilling the contact window opening with a conductive material so as to contact the semiconductor structure for forming the stud.
摘要翻译：通过提供具有对准结构的半导体衬底制造半导体结构的接触柱，该半导体衬底包括侧壁和形成在其上的半导体结构，形成与半导体结构和对准结构的侧壁邻接的侧壁间隔，绝缘层，其与所述侧壁间隔物邻接，以使所述半导体结构绝缘，将所述侧壁间隔物选择性地蚀刻到所述对准结构的侧壁，所述半导体结构和所述绝缘层用于形成用于允许接近所述半导体结构的接触窗口，以及用导电材料回填接触窗口以便接触用于形成螺柱的半导体结构。

10. 发明授权

US5217567A Selective etching process for boron nitride films 失效
标题翻译：氮化硼薄膜的选择性蚀刻工艺
公开(公告)号：US5217567A
公开(公告)日：1993-06-08
申请号：US842663
申请日：1992-02-27
申请人： Donna R. Cote , David M. Dobuzinsky , Son V. Nguyen
发明人： Donna R. Cote , David M. Dobuzinsky , Son V. Nguyen
IPC分类号： H01L21/311 , H01L21/318
CPC分类号： H01L21/318 , H01L21/31116
摘要： Disclosed is a process for etching a film of boron nitride with high selectivity to a layer of silicon dioxide or silicon nitride. The process involves exposing the film to a plasma formed from a mixture of an oxygen-containing gas, such as oxygen, and a small amount of a fluorine-containing gas, such as CF.sub.4. The process provides a high etch rate and anisotropic profiles, as well as good uniformity.
摘要翻译：公开了以高选择性对二氧化硅或氮化硅层蚀刻氮化硼的膜的方法。该方法包括将膜暴露于由含氧气体如氧气和少量含氟气体如CF 4的混合物形成的等离子体。该方法提供了高蚀刻速率和各向异性特性，以及良好的均匀性。

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