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1. 发明申请

US20060226473A1 Gate electrode stack and use of a gate electrode stack 审中-公开
标题翻译：栅极电极堆叠和栅极电极堆叠的使用
公开(公告)号：US20060226473A1
公开(公告)日：2006-10-12
申请号：US11101378
申请日：2005-04-07
申请人： Dongping Wu , Matthias Goldbach , Ulrich Egger
发明人： Dongping Wu , Matthias Goldbach , Ulrich Egger
IPC分类号： H01L29/792
CPC分类号： H01L21/28061 , H01L21/2807 , H01L21/28114 , H01L21/28247 , H01L21/32137 , H01L21/32139 , H01L21/76897 , H01L27/10873 , H01L29/4941 , H01L29/517
摘要： A gate electrode stack is disposed on a substrate in a semiconductor device. A gate conductor includes at least one layer of polysilicon and at least one layer of poly-Si1−x,Gex material. The invention is also concerned with a process. This structure can be etched effectively since an end point detection is enabled.
摘要翻译：栅电极堆叠设置在半导体器件中的衬底上。栅极导体包括至少一层多晶硅和至少一层多晶Si 1-x N，Ge x S x材料。本发明也涉及一个过程。可以有效地蚀刻这种结构，因为启用了终点检测。

2. 发明授权

US07202535B2 Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure 有权
标题翻译：集成半导体结构的制造方法和相应的集成半导体结构
公开(公告)号：US07202535B2
公开(公告)日：2007-04-10
申请号：US11183224
申请日：2005-07-14
申请人： Matthias Goldbach , Dongping Wu
发明人： Matthias Goldbach , Dongping Wu
IPC分类号： H01L29/94
CPC分类号： H01L21/823857
摘要： The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The manufacturing method comprises the steps of: providing a semiconductor substrate (1) having an upper surface (O) and having first and second transistor regions (T1, T2); wherein said first transistor region (T1) is a n-MOSFET region and second transistor region (T2) is a p-MOSFET region; forming a gate structure on said first and second transistor region (T1, T2) including at least one gate dielectric layer (2, 3, 10c, 17, 25) and one gate layer (4; 35; 50, 60) in each of said first and second transistor regions (T1, T2); wherein said gate layer (4; 35; 60) in said second transistor region (T2) is made of negatively doped polysilicon; wherein said at least one gate dielectric layer (2, 10c, 17) in said first transistor region (T1) comprises a first dielectric layer (2, 10c, 17); wherein said at least one gate dielectric layer (2, 3, 10c, 25, 25′) in said second transistor region (T2) comprises an interfacial dielectric layer (2; 25; 25′) located adjacent to said gate layer (4; 35; 60) in said second transistor region (T2), which interfacial dielectric layer (2; 25; 25′) forms an Al2O3 containing interface on said gate layer (4; 35; 60) in said second transistor region (T2) causing a Fermi-pinning effect; and wherein said first transistor region (T1) does not include said interfacial dielectric layer (2; 25; 25′).
摘要翻译：本发明提供了一种用于集成半导体结构和相应的集成半导体结构的制造方法。该制造方法包括以下步骤：提供具有上表面（O）并具有第一和第二晶体管区域（T 1，T 2）的半导体衬底（1）; 其中所述第一晶体管区域（T 1）是n-MOSFET区域，第二晶体管区域（T 2）是p-MOSFET区域; 在包括至少一个栅极介电层（2,3,10c，17,25）和一个栅极层（4; 35; 50,60）的所述第一和第二晶体管区域（T 1，T 2）上形成栅极结构，在所述第一和第二晶体管区域（T 1，T 2）的每一个中; 其中所述第二晶体管区域（T 2）中的所述栅极层（4; 35; 60）由负掺杂多晶硅制成; 其中所述第一晶体管区域（T 1）中的所述至少一个栅介质层（2,10c，17）包括第一介电层（2,10c，17）; 其中所述第二晶体管区域（T 2）中的所述至少一个栅极电介质层（2,3，10c，25,25'）包括邻近所述栅极层的界面电介质层（2; 25; 25'） 4; 35; 60）在所述第二晶体管区域（T 2）中，所述界面电介质层（2; 25; 25'）形成含有Al 2 N 3 O 3界面在所述第二晶体管区域（T 2）中的所述栅极层（4; 35; 60）上引起费米钉扎效应; 并且其中所述第一晶体管区域（T 1）不包括所述界面电介质层（2; 25; 25'）。

3. 发明申请

US20070015325A1 Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure 有权
公开(公告)号：US20070015325A1
公开(公告)日：2007-01-18
申请号：US11183224
申请日：2005-07-14
申请人： Matthias Goldbach , Dongping Wu
发明人： Matthias Goldbach , Dongping Wu
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857
摘要： The present invention provides a manufacturing method for an integrated semiconductor structure and a corresponding integrated semiconductor structure. The manufacturing method comprises the steps of: providing a semiconductor substrate (1) having an upper surface (O) and having first and second transistor regions (T1, T2); wherein said first transistor region (T1) is a n-MOSFET region and second transistor region (T2) is a p-MOSFET region; forming a gate structure on said first and second transistor region (T1, T2) including at least one gate dielectric layer (2, 3, 10c, 17, 25) and one gate layer (4; 35; 50, 60) in each of said first and second transistor regions (T1, T2); wherein said gate layer (4; 35; 60) in said second transistor region (T2) is made of negatively doped polysilicon; wherein said at least one gate dielectric layer (2, 10c, 17) in said first transistor region (T1) comprises a first dielectric layer (2, 10c, 17); wherein said at least one gate dielectric layer (2, 3, 10c, 25, 25′) in said second transistor region (T2) comprises an interfacial dielectric layer (2; 25; 25′) located adjacent to said gate layer (4; 35; 60) in said second transistor region (T2), which interfacial dielectric layer (2; 25; 25′) forms an Al2O3 containing interface on said gate layer (4; 35; 60) in said second transistor region (T2) causing a Fermi-pinning effect; and wherein said first transistor region (T1) does not include said interfacial dielectric layer (2; 25; 25′).

4. 发明申请

US20070187774A1 Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure 审中-公开
标题翻译：集成半导体结构的制造方法和相应的集成半导体结构
公开(公告)号：US20070187774A1
公开(公告)日：2007-08-16
申请号：US11784637
申请日：2007-04-09
申请人： Matthias Goldbach , Dongping Wu
发明人： Matthias Goldbach , Dongping Wu
IPC分类号： H01L29/94
CPC分类号： H01L21/823857
摘要： An integrated semiconductor structure includes an n-channel transistor at a surface of a semiconductor body. The n-channel transistor includes a polysilicon gate overlying a first gate dielectric. A p-channel transistor is also formed at the surface of the semiconductor body. The p-channel transistor includes an n-doped polysilicon gate overlying a second gate dielectric. The second gate dielectric includes an aluminum oxide layer between an underlying dielectric layer and the n-doped polysilicon gate.
摘要翻译：集成半导体结构包括在半导体本体的表面处的n沟道晶体管。 n沟道晶体管包括覆盖第一栅极电介质的多晶硅栅极。在半导体本体的表面也形成p沟道晶体管。 p沟道晶体管包括覆盖第二栅极电介质的n掺杂多晶硅栅极。第二栅极电介质包括在下面的介电层和n掺杂的多晶硅栅极之间的氧化铝层。

5. 发明授权

US07718475B2 Method for manufacturing an integrated circuit including a transistor 有权
标题翻译：一种用于制造包括晶体管的集成电路的方法
公开(公告)号：US07718475B2
公开(公告)日：2010-05-18
申请号：US11786822
申请日：2007-04-13
申请人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
发明人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
IPC分类号： H01L21/335 , H01L29/76
CPC分类号： H01L21/28061 , H01L29/4941 , H01L29/78 , H01L29/7845
摘要： The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.
摘要翻译：本发明涉及一种晶体管，其包括栅极沟道区和具有布置在栅极沟道区上的机械应力的栅极叠层。

6. 发明授权

US07679149B2 Method of removing refractory metal layers and of siliciding contact areas 失效
$Method of removing refractory metal layers and of siliciding contact areas$
标题翻译：去除难熔金属层和硅化接触区域的方法
公开(公告)号：US07679149B2
公开(公告)日：2010-03-16
申请号：US11669500
申请日：2007-01-31
申请人： Audrey Beckert , Matthias Goldbach , Clemens Fitz
发明人： Audrey Beckert , Matthias Goldbach , Clemens Fitz
IPC分类号： H01L29/76
CPC分类号： H01L21/28518 , H01L21/32134 , H01L21/76843 , H01L21/76855 , H01L29/66545 , H01L29/78
摘要： A method of formation of contacts with cobalt silicide since is disclosed. For example, after siliciding with the SOM solution, both unreacted sections of the deposition layer including, for example, cobalt as initial layer for the siliciding and an oxidation protection layer including titanium and deposited by means of cathode beam sputtering, for instance, may be removed rapidly and with high selectivity relative to the cobalt silicide and other, densified metal structures and metal layers.
摘要翻译：公开了一种与硅化钴形成接触的方法。例如，在用SOM溶液硅化后，例如包括例如作为硅化的初始层的钴的钴的沉积层的未反应部分和包括钛并通过阴极射线溅射沉积的氧化保护层可以是相对于硅化钴和其它致密的金属结构和金属层，快速且高选择性地去除。

7. 发明申请

US20080116494A1 Method for manufacturing a semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20080116494A1
公开(公告)日：2008-05-22
申请号：US11602066
申请日：2006-11-20
申请人： Matthias Goldbach , Dietmar Henke , Sven Schmidbauer
发明人： Matthias Goldbach , Dietmar Henke , Sven Schmidbauer
IPC分类号： H01L29/76 , H01L21/265 , H01L21/4763
CPC分类号： H01L21/28518 , H01L21/265 , H01L29/1083 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method for manufacturing a semiconductor device. A silicon substrate comprising at least one structured area in which a dopant is implanted is provided. A contact modifying material is provided on the surface of the at least one structured area. A silicide layer is formed on the surface of the at least one structured area, the silicide layer comprising at least one of titan silicide, titan nitride silicide and cobalt silicide.
摘要翻译：本发明涉及半导体器件的制造方法。提供了包括其中注入掺杂剂的至少一个结构化区域的硅衬底。接触改性材料设置在至少一个结构化区域的表面上。在所述至少一个结构化区域的表面上形成硅化物层，所述硅化物层包括硅化钛，氮化钛硅化物和硅化钴中的至少一种。

8. 发明授权

US07192830B2 Method for fabricating a memory cell 失效
标题翻译：用于制造存储单元的方法
公开(公告)号：US07192830B2
公开(公告)日：2007-03-20
申请号：US10862818
申请日：2004-06-07
申请人： Matthias Goldbach , Thomas Mikolajick , Albert Birner
发明人： Matthias Goldbach , Thomas Mikolajick , Albert Birner
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , H01L21/28273 , H01L29/42332 , H01L29/66825 , H01L29/7887
摘要： Silicon nanocrystals are applied as storage layer (6) and removed using spacer elements (11) laterally with respect to the gate electrode (5). By means of an implantation of dopant, source/drain regions (2) are fabricated in a self-aligned manner with respect to the storage layer (6). The portions of the storage layer (6) are interrupted by the gate electrode (5) and the gate dielectric (4), so that a central portion of the channel region (3) is not covered by the storage layer (6). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.
摘要翻译：将硅纳米晶体作为存储层（6）施加，并且使用间隔元件（11）相对于栅电极（5）横向去除。通过掺杂剂的注入，源极/漏极区域（2）以相对于存储层（6）的自对准方式制造。存储层（6）的部分被栅极（5）和栅极电介质（4）中断，使得沟道区域（3）的中心部分不被存储层（6）覆盖。该存储单元适合作为虚拟地面架构中的多位闪存单元。

9. 发明授权

US07183156B2 Transistor structure, memory cell, DRAM, and method for fabricating a transistor structure in a semiconductor substrate 有权
标题翻译：晶体管结构，存储单元，DRAM以及在半导体衬底中制造晶体管结构的方法
公开(公告)号：US07183156B2
公开(公告)日：2007-02-27
申请号：US10975085
申请日：2004-10-28
申请人： Matthias Goldbach , Ulrich Frey , Björn Fischer
发明人： Matthias Goldbach , Ulrich Frey , Björn Fischer
IPC分类号： H01L21/8242
CPC分类号： H01L27/10888 , H01L27/10855 , H01L27/10867 , H01L27/10873 , H01L29/42368
摘要： Transistor structures, with one source/drain region connected to a charge storage device to be insulated includes an asymmetric gate conductor structure. At a first side wall, which faces the one source/drain region, the asymmetric gate conductor structure has a side wall oxide with a greater thickness and a bird's beak structure with a greater length than at an opposite, second side wall. An effective channel length is increased for the same feature size of the gate conductor structure. Memory cells can be realized in a higher density.
摘要翻译：晶体管结构，具有连接到待绝缘的电荷存储装置的一个源极/漏极区域包括非对称栅极导体结构。在面向一个源极/漏极区域的第一侧壁处，不对称栅极导体结构具有较大厚度的侧壁氧化物和具有比相对的第二侧壁长的长度的鸟嘴结构。对于栅极导体结构的相同特征尺寸，有效沟道长度增加。可以以更高的密度实现存储单元。

10. 发明申请

US20060275981A1 Memory and method for fabricating it 审中-公开
标题翻译：记忆及其制作方法
公开(公告)号：US20060275981A1
公开(公告)日：2006-12-07
申请号：US11442602
申请日：2006-05-30
申请人： Alejandro Avellan , Matthias Goldbach , Thomas Hecht , Stefan Jakschik , Andreas Orth , Uwe Schroder , Michael Stadtmueller , Olaf Storbeck
发明人： Alejandro Avellan , Matthias Goldbach , Thomas Hecht , Stefan Jakschik , Andreas Orth , Uwe Schroder , Michael Stadtmueller , Olaf Storbeck
IPC分类号： H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/10867
摘要： Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.
摘要翻译：存储器及其制造方法在半导体衬底中形成为集成电路并具有存储电容器和开关晶体管的存储器。存储电容器形成在沟槽中的半导体衬底中，并且具有围绕沟槽形成的外部电极层，体现在沟槽壁上的电介质中间层和内部电极层，沟槽是基本上填充，并且开关晶体管形成在表面区域中的半导体衬底中，并且具有第一源极/漏极掺杂区域，第二源极/漏极掺杂区域和中间沟道，其通过绝缘体层与栅电极分离。

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