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1. 发明授权

US07718475B2 Method for manufacturing an integrated circuit including a transistor 有权
标题翻译：一种用于制造包括晶体管的集成电路的方法
公开(公告)号：US07718475B2
公开(公告)日：2010-05-18
申请号：US11786822
申请日：2007-04-13
申请人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
发明人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
IPC分类号： H01L21/335 , H01L29/76
CPC分类号： H01L21/28061 , H01L29/4941 , H01L29/78 , H01L29/7845
摘要： The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.
摘要翻译：本发明涉及一种晶体管，其包括栅极沟道区和具有布置在栅极沟道区上的机械应力的栅极叠层。

2. 发明申请

US20080251815A1 Method for manufacturing a transistor 有权
标题翻译：制造晶体管的方法
公开(公告)号：US20080251815A1
公开(公告)日：2008-10-16
申请号：US11786822
申请日：2007-04-13
申请人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
发明人： Matthias Goldbach , Erhard Landgraf , Michael Stadtmueller , Moritz Haupt , Sven Schmidbauer , Tobias Mono , Jorg Radecker
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28061 , H01L29/4941 , H01L29/78 , H01L29/7845
摘要： The present invention relates to a transistor comprising a gate channel area and a gate stack having mechanical stress arranged on the gate channel area.
摘要翻译：本发明涉及一种晶体管，其包括栅极沟道区和具有布置在栅极沟道区上的机械应力的栅极叠层。

3. 发明申请

US20100078711A1 METHOD OF MANUFACTURING INTEGRATED CIRCUITS INCLUDING A FET WITH A GATE SPACER 有权
标题翻译：制造集成电路的方法，其中包括具有栅极间隔的FET
公开(公告)号：US20100078711A1
公开(公告)日：2010-04-01
申请号：US12242039
申请日：2008-09-30
申请人： Matthias Goldbach , Jessica Hartwich , Lars Dreeskornfeld , Arnd Scholz , Tobias Mono
发明人： Matthias Goldbach , Jessica Hartwich , Lars Dreeskornfeld , Arnd Scholz , Tobias Mono
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.
摘要翻译：一种制造集成电路的方法，该集成电路包括具有栅极间隔物的FET。一个实施例提供了在薄片的相对侧上形成半导体材料的薄片和两个绝缘体结构。薄片凹进。翅片由薄片的中心部分形成。翅片比在翼片的相对侧上彼此面对的薄片的第一和第二部分薄。形成第一间隔结构，其包围翅片的第一部分，第一部分与第一薄片部分相邻。栅电极邻近第一间隔结构设置并且在顶侧和两个相对的侧面上包围翅片的另一部分。

4. 发明申请

US20090057678A1 Method of Forming an Integrated Circuit and Integrated Circuit 审中-公开
标题翻译：形成集成电路和集成电路的方法
公开(公告)号：US20090057678A1
公开(公告)日：2009-03-05
申请号：US11848416
申请日：2007-08-31
申请人： Matthias Goldbach , Erhard Landgraf , Lars Dreeskornfeld
发明人： Matthias Goldbach , Erhard Landgraf , Lars Dreeskornfeld
IPC分类号： H01L29/04 , H01L21/8238
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/3221 , H01L21/324 , H01L21/8238 , H01L21/823814 , H01L21/823892 , H01L29/6659 , H01L29/7833
摘要： A method of forming an integrated circuit, the method including forming at least one patterned gate stack on a substrate including a substrate surface; forming an amorphous substrate region in the substrate by implanting a first material in the substrate; and implanting a getter material to form a getter region within the amorphous substrate region; forming doped implant regions extending from the substrate surface in to the substrate by implanting a second material; and thermally recrystallizing the amorphous substrate region.
摘要翻译：一种形成集成电路的方法，所述方法包括在包括衬底表面的衬底上形成至少一个图案化栅叠层; 通过在衬底中注入第一材料在衬底中形成非晶衬底区域; 以及植入吸气材料以在所述非晶衬底区域内形成吸气剂区域; 通过注入第二材料形成从衬底表面延伸到衬底的掺杂注入区; 并且使非晶衬底区域热重结晶。

5. 发明申请

US20080116494A1 Method for manufacturing a semiconductor device 审中-公开
标题翻译：半导体器件的制造方法
公开(公告)号：US20080116494A1
公开(公告)日：2008-05-22
申请号：US11602066
申请日：2006-11-20
申请人： Matthias Goldbach , Dietmar Henke , Sven Schmidbauer
发明人： Matthias Goldbach , Dietmar Henke , Sven Schmidbauer
IPC分类号： H01L29/76 , H01L21/265 , H01L21/4763
CPC分类号： H01L21/28518 , H01L21/265 , H01L29/1083 , H01L29/665 , H01L29/6659 , H01L29/7833 , H01L2924/0002 , H01L2924/00
摘要： The invention relates to a method for manufacturing a semiconductor device. A silicon substrate comprising at least one structured area in which a dopant is implanted is provided. A contact modifying material is provided on the surface of the at least one structured area. A silicide layer is formed on the surface of the at least one structured area, the silicide layer comprising at least one of titan silicide, titan nitride silicide and cobalt silicide.
摘要翻译：本发明涉及半导体器件的制造方法。提供了包括其中注入掺杂剂的至少一个结构化区域的硅衬底。接触改性材料设置在至少一个结构化区域的表面上。在所述至少一个结构化区域的表面上形成硅化物层，所述硅化物层包括硅化钛，氮化钛硅化物和硅化钴中的至少一种。

6. 发明授权

US07049241B2 Method for forming a trench in a layer or a layer stack on a semiconductor wafer 有权
标题翻译：在半导体晶片上的层或层叠中形成沟槽的方法
公开(公告)号：US07049241B2
公开(公告)日：2006-05-23
申请号：US10937099
申请日：2004-09-08
申请人： Uwe Paul Schroeder , Matthias Goldbach , Tobias Mono
发明人： Uwe Paul Schroeder , Matthias Goldbach , Tobias Mono
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L27/11568 , H01L21/0274 , H01L21/0337 , H01L21/3086 , Y10S438/924
摘要： Preferably using a positive resist, a resist ridge (20) is formed in a photosensitive resist (16) applied on a semiconductor wafer (1) above a hard mask layer (12). The resist ridge (20) serves as a mask for a subsequent implantation step (46). This makes use of an effect whereby the material of the hard mask layer (12), in a part (122) shaded by the resist ridge (20), can be etched out selectively with respect to the implanted part (121). The consequently patterned hard mask layer is used as an etching mask with respect to an underlying layer or layer stack (102–104) that is actually to be patterned. From the resist ridge (10) that has been formed as a line in the photosensitive resist (16), in a type of tone reversal, an opening (24) has been formed in the hard mask layer and a trench (26) has been formed in the layer/layer stack (102–104). According to the invention, the width (51, 52) of the resist ridge (20) is reduced by exposing the resist ridge (20) to an oxygen plasma (42). As a result, it is possible to form a trench (26) in the hard mask layer (12) and in the layer/layer stack (102–104) the width (52) of which trench is smaller than the lithographic resolution limit during the lithographic patterning of the resist (16).
摘要翻译：优选使用正性抗蚀剂，在施加在硬掩模层（12）上方的半导体晶片（1）上的光敏抗蚀剂（16）中形成抗蚀剂脊（20）。抗蚀剂脊（20）用作随后的注入步骤（46）的掩模。这利用了可以相对于植入部分（121）选择性地蚀刻出由抗蚀剂脊（20）遮蔽的部分（122）中的硬掩模层（12）的材料的效果。因此，图案化的硬掩模层相对于实际上被图案化的下层或层叠（102-104）用作蚀刻掩模。从形成为光敏抗蚀剂（16）中的线的抗蚀剂脊（10）以一种音调反转形式，在硬掩模层中形成有开口（24），并且已经形成了沟槽（26）形成在层/层堆叠（102-104）中。根据本发明，通过将抗蚀剂脊（20）暴露于氧等离子体（42）来减小抗蚀剂脊（20）的宽度（51,52）。结果，可以在硬掩模层（12）和层/层堆叠（102-104）中形成沟槽（26），其中沟槽的宽度（52）小于光刻分辨率极限抗蚀剂（16）的平版印刷图案化。

7. 发明申请

US20050106890A1 Method for forming a trench in a layer or a layer stack on a semiconductor wafer 有权
标题翻译：在半导体晶片上的层或层叠中形成沟槽的方法
公开(公告)号：US20050106890A1
公开(公告)日：2005-05-19
申请号：US10937099
申请日：2004-09-08
申请人： Uwe Schroeder , Matthias Goldbach , Tobias Mono
发明人： Uwe Schroeder , Matthias Goldbach , Tobias Mono
IPC分类号： H01L21/027 , H01L21/033 , H01L21/302 , H01L21/308 , H01L21/461 , H01L21/8236 , H01L21/8246 , H01L21/8247
CPC分类号： H01L27/11568 , H01L21/0274 , H01L21/0337 , H01L21/3086 , Y10S438/924
摘要： Preferably using a positive resist, a resist ridge (20) is formed in a photosensitive resist (16) applied on a semiconductor wafer (1) above a hard mask layer (12). The resist ridge (20) serves as a mask for a subsequent implantation step (46). This makes use of an effect whereby the material of the hard mask layer (12), in a part (122) shaded by the resist ridge (20), can be etched out selectively with respect to the implanted part (121). The consequently patterned hard mask layer is used as an etching mask with respect to an underlying layer or layer stack (102-104) that is actually to be patterned. From the resist ridge (10) that has been formed as a line in the photosensitive resist (16), in a type of tone reversal, an opening (24) has been formed in the hard mask layer and a trench (26) has been formed in the layer/layer stack (102-104). According to the invention, the width (51, 52) of the resist ridge (20) is reduced by exposing the resist ridge (20) to an oxygen plasma (42). As a result, it is possible to form a trench (26) in the hard mask layer (12) and in the layer/layer stack (102-104) the width (52) of which trench is smaller than the lithographic resolution limit during the lithographic patterning of the resist (16).
摘要翻译：优选使用正性抗蚀剂，在施加在硬掩模层（12）上方的半导体晶片（1）上的光敏抗蚀剂（16）中形成抗蚀剂脊（20）。抗蚀剂脊（20）用作随后的注入步骤（46）的掩模。这利用了可以相对于植入部分（121）选择性地蚀刻出由抗蚀剂脊（20）遮蔽的部分（122）中的硬掩模层（12）的材料的效果。因此，图案化的硬掩模层相对于实际上被图案化的下层或多层叠层（102-104）用作蚀刻掩模。从形成为光敏抗蚀剂（16）中的线的抗蚀剂脊（10）以一种音调反转形式，在硬掩模层中形成有开口（24），并且已经形成了沟槽（26）形成在层/层堆叠（102-104）中。根据本发明，通过将抗蚀剂脊（20）暴露于氧等离子体（42）来减小抗蚀剂脊（20）的宽度（51,52）。结果，可以在硬掩模层（12）和层/层堆叠（102-104）中形成沟槽（26），其中沟槽的宽度（52）小于光刻分辨率极限抗蚀剂（16）的平版印刷图案化。

8. 发明授权

US07863136B2 Method of manufacturing integrated circuits including a FET with a gate spacer and a fin 有权
标题翻译：制造集成电路的方法，该集成电路包括具有栅极间隔物和鳍的FET
公开(公告)号：US07863136B2
公开(公告)日：2011-01-04
申请号：US12242039
申请日：2008-09-30
申请人： Matthias Goldbach , Jessica Hartwich , Lars Dreeskornfeld , Arnd Scholz , Tobias Mono
发明人： Matthias Goldbach , Jessica Hartwich , Lars Dreeskornfeld , Arnd Scholz , Tobias Mono
IPC分类号： H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A method of manufacturing integrated circuits including a FET with a gate spacer. One embodiment provides forming a lamella of a semiconductor material and two insulator structures on opposing sides of the lamella. The lamella is recessed. A fin is formed from a central portion of the lamella. The fin is thinner than a first and a second portion of the lamella which face each other on opposing sides of the fin. A first spacer structure is formed which encompasses a first portion of the fin, the first portion adjoining to the first lamella portion. A gate electrode is disposed adjacent to the first spacer structure and encompasses a further portion of the fin on a top side and on two opposing lateral sides.
摘要翻译：一种制造集成电路的方法，该集成电路包括具有栅极间隔物的FET。一个实施例提供了在薄片的相对侧上形成半导体材料的薄片和两个绝缘体结构。薄片凹进。翅片由薄片的中心部分形成。翅片比在翼片的相对侧上彼此面对的薄片的第一和第二部分薄。形成第一间隔结构，其包围翅片的第一部分，第一部分与第一薄片部分相邻。栅电极邻近第一间隔结构设置并且在顶侧和两个相对的侧面上包围翅片的另一部分。

9. 发明申请

US20090159976A1 INTEGRATED CIRCUIT AND METHOD FOR MAKING AN INTEGRATED CIRCUIT 审中-公开
标题翻译：集成电路和制造集成电路的方法
公开(公告)号：US20090159976A1
公开(公告)日：2009-06-25
申请号：US11961826
申请日：2007-12-20
申请人： Matthias Goldbach , Tobias Mono
发明人： Matthias Goldbach , Tobias Mono
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/4966 , H01L21/28088 , H01L21/324 , H01L29/4975 , H01L29/517 , H01L29/665 , H01L29/66545 , H01L29/7833
摘要： An integrated circuit comprises a dielectric layer located on a substrate and an electrode located on the dielectric layer. The electrode comprises a first metallic layer located on the dielectric layer and a second metallic layer. Moreover, a method of making an integrated circuit is described.
摘要翻译：集成电路包括位于基板上的电介质层和位于电介质层上的电极。电极包括位于电介质层上的第一金属层和第二金属层。此外，描述了制造集成电路的方法。

10. 发明授权

US07825013B2 Integrated circuit comprising an amorphous region and method of manufacturing an integrated circuit 有权
标题翻译：包括非晶区域的集成电路和制造集成电路的方法
公开(公告)号：US07825013B2
公开(公告)日：2010-11-02
申请号：US12122892
申请日：2008-05-19
申请人： Matthias Goldbach , Dietmar Henke , Sven Schmidbauer
发明人： Matthias Goldbach , Dietmar Henke , Sven Schmidbauer
IPC分类号： H01L21/20 , H01L29/04 , H01L31/20
CPC分类号： H01L21/28518 , H01L21/76814 , H01L21/76889 , H01L29/41766 , H01L29/7833
摘要： An integrated circuit comprises a doped semiconductor portion including an amorphous portion and a contact structure comprising a conductive material. The contact structure is in contact with the amorphous portion. According to another embodiment, an integrated circuit comprises a doped semiconductor portion including a region having a non-stoichiometric composition and a contact structure comprising a conductive material. The contact structure is in contact with the region having a non-stoichiometric composition.
摘要翻译：集成电路包括包括非晶体部分的掺杂半导体部分和包括导电材料的接触结构。接触结构与无定形部分接触。根据另一实施例，集成电路包括掺杂半导体部分，其包括具有非化学计量组成的区域和包括导电材料的接触结构。接触结构与具有非化学计量组成的区域接触。

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