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    • 2. 发明申请
    • FUSED MULTIPLY-ADD APPARATUS AND METHOD
    • 熔融多媒体设备和方法
    • US20120124117A1
    • 2012-05-17
    • US13153885
    • 2011-06-06
    • Hyeong-Seok YuDong-Kwan SuhSuk-Jin KimSan KimYong-Surk Lee
    • Hyeong-Seok YuDong-Kwan SuhSuk-Jin KimSan KimYong-Surk Lee
    • G06F7/487G06F7/485G06F5/01
    • G06F7/483G06F7/5443
    • A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.
    • 提供固定的乘法(FMA)装置和方法。 该FMA装置包括:部分乘积发生器,被配置为产生部分和和部分进位;进位保存加法器,被配置为通过将部分和和相加来产生具有第一位大小的部分和和具有第一位大小的部分进位 部分进位到第三浮点数的尾数的最低有效位(LSB),进位选择加法器,被配置为通过将第一位大小部分和和第一位大小部分相加来生成具有第二位大小的尾数 携带到第三浮点数的最高有效位(MSB),以及选择器,被配置为根据是否将第一位大小部分和和第一位大小部分进位发送到进位存储加法器或进位选择加法器 第三个浮点数的尾数为零。
    • 4. 发明授权
    • Fused multiply-add apparatus and method
    • 熔融多重加法装置及方法
    • US08805915B2
    • 2014-08-12
    • US13153885
    • 2011-06-06
    • Hyeong-Seok YuDong-Kwan SuhSuk-Jin KimSan KimYong-Surk Lee
    • Hyeong-Seok YuDong-Kwan SuhSuk-Jin KimSan KimYong-Surk Lee
    • G06F7/38
    • G06F7/483G06F7/5443
    • A fixed multiply-add (FMA) apparatus and method are provided. The FMA apparatus includes a partial product generator configured to generate a partial sum and a partial carry, a carry save adder configured to generate a partial sum having a first bit size and a partial carry having the first bit size by adding the partial sum and the partial carry to least significant bits (LSBs) of the mantissa of a third floating-point number, a carry select adder configured to generate a mantissa having a second bit size by adding the first bit-size partial sum and the first bit-size partial carry to most significant bits (MSBs) of the third floating-point number, and a selector configured to transmit the first bit-size partial sum and the first bit-size partial carry to the carry save adder or the carry select adder according to whether the mantissa of the third floating-point number is zero.
    • 提供固定的乘法(FMA)装置和方法。 该FMA装置包括:部分乘积发生器,被配置为产生部分和和部分进位;进位保存加法器,被配置为通过将部分和和相加来产生具有第一位大小的部分和和具有第一位大小的部分进位 部分进位到第三浮点数的尾数的最低有效位(LSB),进位选择加法器,被配置为通过将第一位大小部分和和第一位大小部分相加来生成具有第二位大小的尾数 携带到第三浮点数的最高有效位(MSB),以及选择器,被配置为根据是否将第一位大小部分和和第一位大小部分进位发送到进位存储加法器或进位选择加法器 第三个浮点数的尾数为零。